Removed ML401 support
[mw/milkymist.git] / cores /
2010-06-23 lekernelRemoved ML401 support
2010-06-23 lekernelFixed timing problem
2010-06-23 lekernelNew TMU2 cache OK in functional simulation
2010-06-23 lekernelNew TMU cache WIP
2010-06-22 lekernelPFPU working on M1. Added 1 pipeline stage to meet...
2010-06-22 lekernelEthernet working (experimental, random FIFO problems)
2010-06-21 lekernelSDRAM fixes
2010-06-21 lekernelBIOS starting on M1, SDRAM not working
2010-06-19 lekernel16 bit flash support
2010-06-18 lekernelFIFO cleanup
2010-06-18 lekernelTiming OK at 83.33MHz on M1. Modified FIFO design ...
2010-06-16 lekernelProper decay
2010-06-13 lekernelTMU color rounding, with nearest even tie resolution
2010-05-18 lekernelIncrease Minimac FIFO sizes. This tickles yet another...
2010-05-17 lekernelRemove BRAM core
2010-05-11 lekernelDouble texel cache, enable Minimac by default (timing...
2010-05-07 lekernelPFPU HW doc
2010-05-04 lekernelFull texel cache results
2010-05-04 lekernelTMU cache performance measurement + report
2010-04-18 lekernelTMU doc update Release_0.5
2010-04-08 lekernelCleanup TMU2 simulation makefile
2010-04-07 lekernelNew FML arbiter, fixed DRAM write-to-read timing, alpha...
2010-04-07 lekernelTMU test bench with arbiter
2010-04-06 lekernelAlmost working
2010-04-06 lekernelIntegration
2010-04-06 lekernelAlpha blending working in simulation
2010-04-06 lekernelAlpha blending in TMU2, not integrated, not fully tested
2010-04-03 lekernelNew PFPU instructions, untested
2010-03-21 lekernelFix typo in sysctl.tex (address of capabilities registe...
2010-03-20 lekernelCapabilities register
2010-03-13 lekernelrestore permissions
2010-03-13 lekernelFML meter doc
2010-03-11 lekernelMemory performance results
2010-03-11 lekernelFML meter
2010-03-06 lekernelTMU2 interpolation bugfix
2010-03-06 lekernelMinimac doc
2010-03-03 lekernelEthernet TX working
2010-03-03 lekernelEthernet TX (untested)
2010-03-02 lekernelcleanup
2010-03-02 lekernelRX working (but need to use Synplify instead of Xilinx...
2010-03-02 lekernelminimac fixes
2010-03-01 lekernelEthernet RX (does not work yet)
2010-02-28 lekernelMDIO R/W working
2010-02-28 lekernelMinimac ctlif, untested
2010-02-27 lekernelMinimac interface
2010-02-18 lekernelPFPU doc update Release_0.3
2010-02-18 lekernelTMU2 documentation
2010-02-16 lekernelFixes + hack for picture brightness
2010-02-15 lekernelSimpler and smaller PFPU DMA engine
2010-02-15 lekernelImproved PFPU timing + SW fixes
2010-02-15 lekernelNew PFPU
2010-02-15 lekernelcleanup
2010-02-15 lekernelDecay module cleanup + display speed info
2010-02-15 lekernelFixed clamp unit
2010-02-15 lekernelnew write buffer doesnt work, simulators and synthesize...
2010-02-15 lekernelwrite buffer tb
2010-02-14 lekernelWrite buffer fix
2010-02-14 lekernelFixed CE pin on multipliers + iverilog support
2010-02-14 lekernelNew write buffer WIP
2010-02-14 lekernelworkarounds for synthesizer problems
2010-02-14 lekernelTMU2 working on HW with some artefacts
2010-02-14 lekernelFix DSP48 configuration
2010-02-14 lekernelModel using DSP48 primitives to work around Xst bugs
2010-02-13 lekernelUse the new TMU in synthesis
2010-02-13 lekernelBilinear filtering OK in simulation
2010-02-13 lekernelBlend unit
2010-02-13 lekernelCrazyness working
2010-02-13 lekernelFurther bugfix
2010-02-13 lekernelMore bugs gone
2010-02-12 lekernelFix WIP
2010-02-12 lekernelMore bugfix
2010-02-12 lekernelfixes
2010-02-12 lekernelsyntax fixg
2010-02-12 lekernelTexel cache, untested
2010-02-12 lekernelParametrizable memory
2010-02-12 lekernelAddress generator + RAM elements
2010-02-09 lekernelUnsigned numbers
2010-02-09 lekernelmask + clamp
2010-02-09 lekernelUse only blocking assignment
2010-02-09 lekernelAvoid Verilog trap (thanks Paul Campbell for pointing...
2010-02-09 lekernelHorizontal interpolation working
2010-02-08 lekernelHorizontal interpolation WIP
2010-02-08 lekernelVertical interpolation OK
2010-02-08 lekernelVertical interpolation bugfix WIP
2010-02-08 lekernelVertical interpolation bugfix WIP
2010-02-02 lekernelconnected, syntax ok, not working
2010-02-02 lekernelVertical interpolation
2010-02-02 lekernelVDIV
2010-02-02 lekernelvdivops stage + tb
2010-02-02 lekernelVertex fetch OK in simulation
2010-02-02 lekernelBeginning of new TMU
2010-01-31 lekernelCache coherent transactions working
2010-01-31 lekernelfixes
2010-01-31 lekernelPS/2 fix
2010-01-31 lekernelCache coherent VGA transactions, untested
2010-01-31 lekernelmissing file
2010-01-31 lekernelDirect cache bus support in fmlbrg, untested
2010-01-30 lekernelSDRAM timing fixes from Zeus
2010-01-13 lekernelNew reset system
2010-01-13 lekernelEthernet working
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