change includes to use new csr base address
[mw/milkymist.git] / cores / tmu2 /
2010-06-28 lekernelBugfixes in VPI image module
2010-06-28 lekernelcleanup
2010-06-28 lekernelRemoved Virtex4 support in TMU simulation
2010-06-25 lekernelRemoved unneeded file
2010-06-24 lekernelBigger texel cache
2010-06-23 lekernelFixed timing problem
2010-06-23 lekernelNew TMU2 cache OK in functional simulation
2010-06-23 lekernelNew TMU cache WIP
2010-06-16 lekernelProper decay
2010-06-13 lekernelTMU color rounding, with nearest even tie resolution
2010-05-17 lekernelRemove BRAM core
2010-05-11 lekernelDouble texel cache, enable Minimac by default (timing...
2010-05-04 lekernelFull texel cache results
2010-05-04 lekernelTMU cache performance measurement + report
2010-04-18 lekernelTMU doc update Release_0.5
2010-04-08 lekernelCleanup TMU2 simulation makefile
2010-04-07 lekernelNew FML arbiter, fixed DRAM write-to-read timing, alpha...
2010-04-07 lekernelTMU test bench with arbiter
2010-04-06 lekernelIntegration
2010-04-06 lekernelAlpha blending working in simulation
2010-04-06 lekernelAlpha blending in TMU2, not integrated, not fully tested
2010-03-06 lekernelTMU2 interpolation bugfix
2010-02-18 lekernelTMU2 documentation
2010-02-15 lekernelcleanup
2010-02-15 lekernelDecay module cleanup + display speed info
2010-02-15 lekernelFixed clamp unit
2010-02-15 lekernelnew write buffer doesnt work, simulators and synthesize...
2010-02-15 lekernelwrite buffer tb
2010-02-14 lekernelWrite buffer fix
2010-02-14 lekernelFixed CE pin on multipliers + iverilog support
2010-02-14 lekernelNew write buffer WIP
2010-02-14 lekernelworkarounds for synthesizer problems
2010-02-14 lekernelTMU2 working on HW with some artefacts
2010-02-14 lekernelFix DSP48 configuration
2010-02-14 lekernelModel using DSP48 primitives to work around Xst bugs
2010-02-13 lekernelUse the new TMU in synthesis
2010-02-13 lekernelBilinear filtering OK in simulation
2010-02-13 lekernelBlend unit
2010-02-13 lekernelCrazyness working
2010-02-13 lekernelFurther bugfix
2010-02-13 lekernelMore bugs gone
2010-02-12 lekernelFix WIP
2010-02-12 lekernelMore bugfix
2010-02-12 lekernelfixes
2010-02-12 lekernelsyntax fixg
2010-02-12 lekernelTexel cache, untested
2010-02-12 lekernelParametrizable memory
2010-02-12 lekernelAddress generator + RAM elements
2010-02-09 lekernelUnsigned numbers
2010-02-09 lekernelmask + clamp
2010-02-09 lekernelUse only blocking assignment
2010-02-09 lekernelAvoid Verilog trap (thanks Paul Campbell for pointing...
2010-02-09 lekernelHorizontal interpolation working
2010-02-08 lekernelHorizontal interpolation WIP
2010-02-08 lekernelVertical interpolation OK
2010-02-08 lekernelVertical interpolation bugfix WIP
2010-02-08 lekernelVertical interpolation bugfix WIP
2010-02-02 lekernelconnected, syntax ok, not working
2010-02-02 lekernelVertical interpolation
2010-02-02 lekernelVDIV
2010-02-02 lekernelvdivops stage + tb
2010-02-02 lekernelVertex fetch OK in simulation
2010-02-02 lekernelBeginning of new TMU