Fixed norflash8
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Sun, 23 Aug 2009 18:48:34 +0000 (20:48 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Sun, 23 Aug 2009 18:48:34 +0000 (20:48 +0200)
milkymist-core/cores/norflash8/rtl/norflash8.v
milkymist-core/cores/norflash8/test/Makefile [new file with mode: 0644]
milkymist-core/cores/norflash8/test/tb_norflash8.v [new file with mode: 0644]

index fb4673d..0ab6f8f 100644 (file)
@@ -39,6 +39,7 @@ reg [1:0] flash_adr_lsb;
 assign flash_adr = {flash_adr_msb, flash_adr_lsb};
 
 reg load;
+reg reset_flash_adr_lsb;
 always @(posedge sys_clk) begin
        /* Use IOB registers to prevent glitches on address lines */
        if(wb_cyc_i & wb_stb_i) /* register only when needed to reduce EMI */
@@ -52,6 +53,8 @@ always @(posedge sys_clk) begin
                endcase
                flash_adr_lsb <= flash_adr_lsb + 2'd1;
        end
+       if(reset_flash_adr_lsb)
+               flash_adr_lsb <= 2'd0;
 end
 
 /*
@@ -71,8 +74,8 @@ always @(posedge sys_clk) begin
        end
 end
 
-reg state;
-reg next_state;
+reg [1:0] state;
+reg [1:0] next_state;
 always @(posedge sys_clk) begin
        if(sys_rst)
                state <= 1'b0;
@@ -82,26 +85,31 @@ end
 
 always @(*) begin
        next_state = state;
+       reset_flash_adr_lsb = 1'b0;
        counter_en = 1'b0;
        load = 1'b0;
        wb_ack_o = 1'b0;
 
        case(state)
-               1'b0: begin
+               2'd0: begin
+                       reset_flash_adr_lsb = 1'b1;
                        if(wb_cyc_i & wb_stb_i)
-                               next_state = 1'b1;
+                               next_state = 2'd1;
                end
 
-               1'b1: begin
+               2'd1: begin
                        counter_en = 1'b1;
                        if(counter_done) begin
                                load = 1'b1;
-                               if(flash_adr_lsb == 2'b11) begin
-                                       wb_ack_o = 1'b1;
-                                       next_state = 1'b0;
-                               end
+                               if(flash_adr_lsb == 2'b11)
+                                       next_state = 2'd2;
                        end
                end
+
+               2'd2: begin
+                       wb_ack_o = 1'b1;
+                       next_state = 2'd0;
+               end
        endcase
 end
 
diff --git a/milkymist-core/cores/norflash8/test/Makefile b/milkymist-core/cores/norflash8/test/Makefile
new file mode 100644 (file)
index 0000000..d36419e
--- /dev/null
@@ -0,0 +1,17 @@
+SOURCES=tb_norflash8.v $(wildcard ../rtl/*.v)
+
+all: tb_norflash8
+
+sim: tb_norflash8
+       ./tb_norflash8
+
+cversim: $(SOURCES)
+       cver $(SOURCES)
+
+clean:
+       rm -f tb_norflash8 verilog.log norflash8.vcd
+
+tb_norflash8: $(SOURCES)
+       iverilog -o tb_norflash8 $(SOURCES)
+
+.PHONY: clean sim cversim
diff --git a/milkymist-core/cores/norflash8/test/tb_norflash8.v b/milkymist-core/cores/norflash8/test/tb_norflash8.v
new file mode 100644 (file)
index 0000000..172d1c2
--- /dev/null
@@ -0,0 +1,107 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ *
+ * This program is free and excepted software; you can use it, redistribute it
+ * and/or modify it under the terms of the Exception General Public License as
+ * published by the Exception License Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
+ * details.
+ *
+ * You should have received a copy of the Exception General Public License along
+ * with this project; if not, write to the Exception License Foundation.
+ */
+
+`timescale 1ns / 1ps
+
+module tb_norflash8();
+
+reg sys_clk;
+reg sys_rst;
+
+reg [31:0] wb_adr_i;
+wire [31:0] wb_dat_o;
+reg wb_cyc_i;
+reg wb_stb_i;
+wire wb_ack_o;
+
+wire [6:0] aceusb_a;
+wire [15:0] aceusb_d;
+
+wire [21:0] flash_adr;
+reg [7:0] flash_d;
+
+always @(flash_adr) #110 flash_d <= flash_adr[7:0] + 8'd1;
+
+norflash8 dut(
+       .sys_clk(sys_clk),
+       .sys_rst(sys_rst),
+
+       .wb_adr_i(wb_adr_i),
+       .wb_dat_o(wb_dat_o),
+       .wb_cyc_i(wb_cyc_i),
+       .wb_stb_i(wb_stb_i),
+       .wb_ack_o(wb_ack_o),
+
+       .flash_adr(flash_adr),
+       .flash_d(flash_d)
+);
+
+task wbread;
+       input [31:0] address;
+       integer i;
+       begin
+               wb_adr_i = address;
+               wb_cyc_i = 1'b1;
+               wb_stb_i = 1'b1;
+               
+               i = 1;
+               while(~wb_ack_o) begin
+                       #5 sys_clk = 1'b1;
+                       #5 sys_clk = 1'b0;
+                       i = i + 1;
+               end
+               
+               $display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
+               
+               /* Let the core release its ack */
+               #5 sys_clk = 1'b1;
+               #5 sys_clk = 1'b0;
+               
+               wb_cyc_i = 1'b0;
+               wb_stb_i = 1'b0;
+       end
+endtask
+
+initial begin
+       sys_rst = 1'b1;
+       sys_clk = 1'b0;
+       
+       wb_adr_i = 32'h00000000;
+       wb_cyc_i = 1'b0;
+       wb_stb_i = 1'b0;
+
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       
+       sys_rst = 1'b0;
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       
+       wbread(32'h00000020);
+       wbread(32'h00000010);
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       wbread(32'h00000040);
+       
+       $finish;
+end
+
+endmodule
+