HPDMC on S6, untested
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Mon, 7 Sep 2009 10:09:45 +0000 (12:09 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Mon, 7 Sep 2009 10:09:45 +0000 (12:09 +0200)
milkymist-core/boards/milkymist-one/rtl/ddram.v
milkymist-core/boards/xilinx-ml401/rtl/ddram.v
milkymist-core/cores/hpdmc_ddr32/rtl/hpdmc.v
milkymist-core/cores/hpdmc_ddr32/rtl/hpdmc_ddrio.v [deleted file]
milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v [new file with mode: 0644]
milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_iddr32.v
milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr32.v
milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_oddr4.v
milkymist-core/cores/hpdmc_ddr32/rtl/virtex4/hpdmc_ddrio.v [new file with mode: 0644]

index 10dd676..07bf94c 100644 (file)
@@ -164,6 +164,7 @@ hpdmc #(
        .sdram_columndepth(`SDRAM_COLUMNDEPTH)
 ) hpdmc (
        .sys_clk(sys_clk),
+       .sys_clk_n(~sys_clk),
        .dqs_clk(dqs_clk),
        .sys_rst(sys_rst),
 
index 10dd676..c6b0f9e 100644 (file)
@@ -164,6 +164,7 @@ hpdmc #(
        .sdram_columndepth(`SDRAM_COLUMNDEPTH)
 ) hpdmc (
        .sys_clk(sys_clk),
+       .sys_clk_n(1'b0), /* < not needed on Virtex-4 */
        .dqs_clk(dqs_clk),
        .sys_rst(sys_rst),
 
index c90b956..052d1b9 100644 (file)
@@ -30,6 +30,7 @@ module hpdmc #(
        parameter sdram_columndepth = 9
 ) (
        input sys_clk,
+       input sys_clk_n,
        /*
         * Clock used to generate DQS.
         * Typically sys_clk phased out by 90 degrees,
@@ -270,6 +271,7 @@ hpdmc_datactl datactl(
 /* Data path */
 hpdmc_ddrio ddrio(
        .sys_clk(sys_clk),
+       .sys_clk_n(sys_clk_n),
        .dqs_clk(dqs_clk),
        
        .direction(direction),
diff --git a/milkymist-core/cores/hpdmc_ddr32/rtl/hpdmc_ddrio.v b/milkymist-core/cores/hpdmc_ddr32/rtl/hpdmc_ddrio.v
deleted file mode 100644 (file)
index a3ae211..0000000
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free and excepted software; you can use it, redistribute it
- * and/or modify it under the terms of the Exception General Public License as
- * published by the Exception License Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
- * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
- * details.
- *
- * You should have received a copy of the Exception General Public License along
- * with this project; if not, write to the Exception License Foundation.
- */
-
-module hpdmc_ddrio(
-       input sys_clk,
-       input dqs_clk,
-       
-       input direction,
-       input [7:0] mo,
-       input [63:0] do,
-       output [63:0] di,
-       
-       output [3:0] sdram_dqm,
-       inout [31:0] sdram_dq,
-       inout [3:0] sdram_dqs,
-       
-       input idelay_rst,
-       input idelay_ce,
-       input idelay_inc
-);
-
-wire [31:0] sdram_data_out;
-assign sdram_dq = direction ? sdram_data_out : 32'hzzzzzzzz;
-assign sdram_dqs = direction ? {4{dqs_clk}} : 4'hz;
-
-hpdmc_oddr4 oddr_dqm(
-       .Q(sdram_dqm),
-       .C(sys_clk),
-       .CE(1'b1),
-       .D1(mo[7:4]),
-       .D2(mo[3:0]),
-       .R(1'b0),
-       .S(1'b0)
-);
-
-hpdmc_oddr32 oddr_dq(
-       .Q(sdram_data_out),
-       .C(sys_clk),
-       .CE(1'b1),
-       .D1(do[63:32]),
-       .D2(do[31:0]),
-       .R(1'b0),
-       .S(1'b0)
-);
-
-wire [31:0] sdram_dq_delayed;
-
-hpdmc_idelay8 dq_delay0 (
-       .i(sdram_dq[7:0]),
-       .o(sdram_dq_delayed[7:0]),
-       
-       .clk(sys_clk),
-       .rst(idelay_rst),
-       .ce(idelay_ce),
-       .inc(idelay_inc)
-);
-hpdmc_idelay8 dq_delay1 (
-       .i(sdram_dq[15:8]),
-       .o(sdram_dq_delayed[15:8]),
-       
-       .clk(sys_clk),
-       .rst(idelay_rst),
-       .ce(idelay_ce),
-       .inc(idelay_inc)
-);
-hpdmc_idelay8 dq_delay2 (
-       .i(sdram_dq[23:16]),
-       .o(sdram_dq_delayed[23:16]),
-       
-       .clk(sys_clk),
-       .rst(idelay_rst),
-       .ce(idelay_ce),
-       .inc(idelay_inc)
-);
-hpdmc_idelay8 dq_delay3 (
-       .i(sdram_dq[31:24]),
-       .o(sdram_dq_delayed[31:24]),
-       
-       .clk(sys_clk),
-       .rst(idelay_rst),
-       .ce(idelay_ce),
-       .inc(idelay_inc)
-);
-
-hpdmc_iddr32 iddr_dq(
-       .Q1(di[31:0]),
-       .Q2(di[63:32]),
-       .C(sys_clk),
-       .CE(1'b1),
-       .D(sdram_dq_delayed),
-       .R(1'b0),
-       .S(1'b0)
-);
-
-endmodule
diff --git a/milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v b/milkymist-core/cores/hpdmc_ddr32/rtl/spartan6/hpdmc_ddrio.v
new file mode 100644 (file)
index 0000000..242936e
--- /dev/null
@@ -0,0 +1,114 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ *
+ * This program is free and excepted software; you can use it, redistribute it
+ * and/or modify it under the terms of the Exception General Public License as
+ * published by the Exception License Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
+ * details.
+ *
+ * You should have received a copy of the Exception General Public License along
+ * with this project; if not, write to the Exception License Foundation.
+ */
+
+module hpdmc_ddrio(
+       input sys_clk,
+       input sys_clk_n,
+       input dqs_clk,
+       
+       input direction,
+       input [7:0] mo,
+       input [63:0] do,
+       output [63:0] di,
+       
+       output [3:0] sdram_dqm,
+       inout [31:0] sdram_dq,
+       inout [3:0] sdram_dqs,
+       
+       input idelay_rst,
+       input idelay_ce,
+       input idelay_inc
+);
+
+wire [31:0] sdram_data_out;
+assign sdram_dq = direction ? sdram_data_out : 32'hzzzzzzzz;
+assign sdram_dqs = direction ? {4{dqs_clk}} : 4'hz;
+
+hpdmc_oddr4 oddr_dqm(
+       .Q(sdram_dqm),
+       .C0(sys_clk),
+       .C1(sys_clk_n),
+       .CE(1'b1),
+       .D0(mo[7:4]),
+       .D1(mo[3:0]),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+hpdmc_oddr32 oddr_dq(
+       .Q(sdram_data_out),
+       .C0(sys_clk),
+       .C1(sys_clk_n),
+       .CE(1'b1),
+       .D0(do[63:32]),
+       .D1(do[31:0]),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+wire [31:0] sdram_dq_delayed;
+
+hpdmc_idelay8 dq_delay0 (
+       .i(sdram_dq[7:0]),
+       .o(sdram_dq_delayed[7:0]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay1 (
+       .i(sdram_dq[15:8]),
+       .o(sdram_dq_delayed[15:8]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay2 (
+       .i(sdram_dq[23:16]),
+       .o(sdram_dq_delayed[23:16]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay3 (
+       .i(sdram_dq[31:24]),
+       .o(sdram_dq_delayed[31:24]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+
+hpdmc_iddr32 iddr_dq(
+       .Q0(di[31:0]),
+       .Q1(di[63:32]),
+       .C0(sys_clk),
+       .C1(sys_clk_n),
+       .CE(1'b1),
+       .D(sdram_dq_delayed),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+endmodule
index eb19e0a..0df88bf 100644 (file)
 
 /*
  * Verilog code that really should be replaced with a generate
- * statement, but free simulators won't let me do.
- * So I put it in a module so as not to make other code unreadable.
+ * statement, but it does not work with some free simulators.
+ * So I put it in a module so as not to make other code unreadable,
+ * and keep compatibility with as many simulators as possible.
  */
 
 module hpdmc_iddr32 #(
-       parameter DDR_CLK_EDGE = "SAME_EDGE",
-       parameter INIT_Q1 = 1'b0,
-       parameter INIT_Q2 = 1'b0,
+       parameter DDR_ALIGNMENT = "C0",
+       parameter INIT_Q0 = 1'b0,
+       parameter INIT_Q0 = 1'b0,
        parameter SRTYPE = "SYNC"
 ) (
+       output [31:0] Q0,
        output [31:0] Q1,
-       output [31:0] Q2,
-       input C,
+       input C0,
+       input C1,
        input CE,
        input [31:0] D,
        input R,
        input S
 );
 
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr0 (
-       .Q1(Q1[0]),
-       .Q2(Q2[0]),
-       .C(C),
+       .Q0(Q0[0]),
+       .Q0(Q1[0]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[0]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr1 (
-       .Q1(Q1[1]),
-       .Q2(Q2[1]),
-       .C(C),
+       .Q0(Q0[1]),
+       .Q0(Q1[1]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[1]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr2 (
-       .Q1(Q1[2]),
-       .Q2(Q2[2]),
-       .C(C),
+       .Q0(Q0[2]),
+       .Q0(Q1[2]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[2]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr3 (
-       .Q1(Q1[3]),
-       .Q2(Q2[3]),
-       .C(C),
+       .Q0(Q0[3]),
+       .Q0(Q1[3]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[3]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr4 (
-       .Q1(Q1[4]),
-       .Q2(Q2[4]),
-       .C(C),
+       .Q0(Q0[4]),
+       .Q0(Q1[4]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[4]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr5 (
-       .Q1(Q1[5]),
-       .Q2(Q2[5]),
-       .C(C),
+       .Q0(Q0[5]),
+       .Q0(Q1[5]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[5]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr6 (
-       .Q1(Q1[6]),
-       .Q2(Q2[6]),
-       .C(C),
+       .Q0(Q0[6]),
+       .Q0(Q1[6]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[6]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr7 (
-       .Q1(Q1[7]),
-       .Q2(Q2[7]),
-       .C(C),
+       .Q0(Q0[7]),
+       .Q0(Q1[7]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[7]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr8 (
-       .Q1(Q1[8]),
-       .Q2(Q2[8]),
-       .C(C),
+       .Q0(Q0[8]),
+       .Q0(Q1[8]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[8]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr9 (
-       .Q1(Q1[9]),
-       .Q2(Q2[9]),
-       .C(C),
+       .Q0(Q0[9]),
+       .Q0(Q1[9]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[9]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr10 (
-       .Q1(Q1[10]),
-       .Q2(Q2[10]),
-       .C(C),
+       .Q0(Q0[10]),
+       .Q0(Q1[10]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[10]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr11 (
-       .Q1(Q1[11]),
-       .Q2(Q2[11]),
-       .C(C),
+       .Q0(Q0[11]),
+       .Q0(Q1[11]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[11]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr12 (
-       .Q1(Q1[12]),
-       .Q2(Q2[12]),
-       .C(C),
+       .Q0(Q0[12]),
+       .Q0(Q1[12]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[12]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr13 (
-       .Q1(Q1[13]),
-       .Q2(Q2[13]),
-       .C(C),
+       .Q0(Q0[13]),
+       .Q0(Q1[13]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[13]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr14 (
-       .Q1(Q1[14]),
-       .Q2(Q2[14]),
-       .C(C),
+       .Q0(Q0[14]),
+       .Q0(Q1[14]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[14]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr15 (
-       .Q1(Q1[15]),
-       .Q2(Q2[15]),
-       .C(C),
+       .Q0(Q0[15]),
+       .Q0(Q1[15]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[15]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr16 (
-       .Q1(Q1[16]),
-       .Q2(Q2[16]),
-       .C(C),
+       .Q0(Q0[16]),
+       .Q0(Q1[16]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[16]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr17 (
-       .Q1(Q1[17]),
-       .Q2(Q2[17]),
-       .C(C),
+       .Q0(Q0[17]),
+       .Q0(Q1[17]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[17]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr18 (
-       .Q1(Q1[18]),
-       .Q2(Q2[18]),
-       .C(C),
+       .Q0(Q0[18]),
+       .Q0(Q1[18]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[18]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr19 (
-       .Q1(Q1[19]),
-       .Q2(Q2[19]),
-       .C(C),
+       .Q0(Q0[19]),
+       .Q0(Q1[19]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[19]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr20 (
-       .Q1(Q1[20]),
-       .Q2(Q2[20]),
-       .C(C),
+       .Q0(Q0[20]),
+       .Q0(Q1[20]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[20]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr21 (
-       .Q1(Q1[21]),
-       .Q2(Q2[21]),
-       .C(C),
+       .Q0(Q0[21]),
+       .Q0(Q1[21]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[21]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr22 (
-       .Q1(Q1[22]),
-       .Q2(Q2[22]),
-       .C(C),
+       .Q0(Q0[22]),
+       .Q0(Q1[22]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[22]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr23 (
-       .Q1(Q1[23]),
-       .Q2(Q2[23]),
-       .C(C),
+       .Q0(Q0[23]),
+       .Q0(Q1[23]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[23]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr24 (
-       .Q1(Q1[24]),
-       .Q2(Q2[24]),
-       .C(C),
+       .Q0(Q0[24]),
+       .Q0(Q1[24]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[24]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr25 (
-       .Q1(Q1[25]),
-       .Q2(Q2[25]),
-       .C(C),
+       .Q0(Q0[25]),
+       .Q0(Q1[25]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[25]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr26 (
-       .Q1(Q1[26]),
-       .Q2(Q2[26]),
-       .C(C),
+       .Q0(Q0[26]),
+       .Q0(Q1[26]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[26]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr27 (
-       .Q1(Q1[27]),
-       .Q2(Q2[27]),
-       .C(C),
+       .Q0(Q0[27]),
+       .Q0(Q1[27]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[27]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr28 (
-       .Q1(Q1[28]),
-       .Q2(Q2[28]),
-       .C(C),
+       .Q0(Q0[28]),
+       .Q0(Q1[28]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[28]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr29 (
-       .Q1(Q1[29]),
-       .Q2(Q2[29]),
-       .C(C),
+       .Q0(Q0[29]),
+       .Q0(Q1[29]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[29]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr30 (
-       .Q1(Q1[30]),
-       .Q2(Q2[30]),
-       .C(C),
+       .Q0(Q0[30]),
+       .Q0(Q1[30]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[30]),
        .R(R),
        .S(S)
 );
-IDDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
-       .INIT_Q1(INIT_Q1),
-       .INIT_Q2(INIT_Q2),
+IDDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
+       .INIT_Q0(INIT_Q0),
+       .INIT_Q0(INIT_Q0),
        .SRTYPE(SRTYPE)
 ) iddr31 (
-       .Q1(Q1[31]),
-       .Q2(Q2[31]),
-       .C(C),
+       .Q0(Q0[31]),
+       .Q0(Q1[31]),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
        .D(D[31]),
        .R(R),
index 1822385..62c3812 100644 (file)
  */
 
 module hpdmc_oddr32 #(
-       parameter DDR_CLK_EDGE = "SAME_EDGE",
+       parameter DDR_ALIGNMENT = "C0",
        parameter INIT = 1'b0,
        parameter SRTYPE = "SYNC"
 ) (
        output [31:0] Q,
-       input C,
+       input C0,
+       input C1,
        input CE,
+       input [31:0] D0,
        input [31:0] D1,
-       input [31:0] D2,
        input R,
        input S
 );
 
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr0 (
        .Q(Q[0]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[0]),
        .D1(D1[0]),
-       .D2(D2[0]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr1 (
        .Q(Q[1]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[1]),
        .D1(D1[1]),
-       .D2(D2[1]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr2 (
        .Q(Q[2]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[2]),
        .D1(D1[2]),
-       .D2(D2[2]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr3 (
        .Q(Q[3]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[3]),
        .D1(D1[3]),
-       .D2(D2[3]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr4 (
        .Q(Q[4]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[4]),
        .D1(D1[4]),
-       .D2(D2[4]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr5 (
        .Q(Q[5]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[5]),
        .D1(D1[5]),
-       .D2(D2[5]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr6 (
        .Q(Q[6]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[6]),
        .D1(D1[6]),
-       .D2(D2[6]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr7 (
        .Q(Q[7]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[7]),
        .D1(D1[7]),
-       .D2(D2[7]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr8 (
        .Q(Q[8]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[8]),
        .D1(D1[8]),
-       .D2(D2[8]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr9 (
        .Q(Q[9]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[9]),
        .D1(D1[9]),
-       .D2(D2[9]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr10 (
        .Q(Q[10]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[10]),
        .D1(D1[10]),
-       .D2(D2[10]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr11 (
        .Q(Q[11]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[11]),
        .D1(D1[11]),
-       .D2(D2[11]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr12 (
        .Q(Q[12]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[12]),
        .D1(D1[12]),
-       .D2(D2[12]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr13 (
        .Q(Q[13]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[13]),
        .D1(D1[13]),
-       .D2(D2[13]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr14 (
        .Q(Q[14]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[14]),
        .D1(D1[14]),
-       .D2(D2[14]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr15 (
        .Q(Q[15]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[15]),
        .D1(D1[15]),
-       .D2(D2[15]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr16 (
        .Q(Q[16]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[16]),
        .D1(D1[16]),
-       .D2(D2[16]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr17 (
        .Q(Q[17]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[17]),
        .D1(D1[17]),
-       .D2(D2[17]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr18 (
        .Q(Q[18]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[18]),
        .D1(D1[18]),
-       .D2(D2[18]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr19 (
        .Q(Q[19]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[19]),
        .D1(D1[19]),
-       .D2(D2[19]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr20 (
        .Q(Q[20]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[20]),
        .D1(D1[20]),
-       .D2(D2[20]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr21 (
        .Q(Q[21]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[21]),
        .D1(D1[21]),
-       .D2(D2[21]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr22 (
        .Q(Q[22]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[22]),
        .D1(D1[22]),
-       .D2(D2[22]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr23 (
        .Q(Q[23]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[23]),
        .D1(D1[23]),
-       .D2(D2[23]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr24 (
        .Q(Q[24]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[24]),
        .D1(D1[24]),
-       .D2(D2[24]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr25 (
        .Q(Q[25]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[25]),
        .D1(D1[25]),
-       .D2(D2[25]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr26 (
        .Q(Q[26]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[26]),
        .D1(D1[26]),
-       .D2(D2[26]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr27 (
        .Q(Q[27]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[27]),
        .D1(D1[27]),
-       .D2(D2[27]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr28 (
        .Q(Q[28]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[28]),
        .D1(D1[28]),
-       .D2(D2[28]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr29 (
        .Q(Q[29]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[29]),
        .D1(D1[29]),
-       .D2(D2[29]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr30 (
        .Q(Q[30]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[30]),
        .D1(D1[30]),
-       .D2(D2[30]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr31 (
        .Q(Q[31]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[31]),
        .D1(D1[31]),
-       .D2(D2[31]),
        .R(R),
        .S(S)
 );
index b0ae174..1db714f 100644 (file)
  */
 
 module hpdmc_oddr4 #(
-       parameter DDR_CLK_EDGE = "SAME_EDGE",
+       parameter DDR_ALIGNMENT = "C0",
        parameter INIT = 1'b0,
        parameter SRTYPE = "SYNC"
 ) (
        output [3:0] Q,
-       input C,
+       input C0,
+       input C1,
        input CE,
+       input [3:0] D0,
        input [3:0] D1,
-       input [3:0] D2,
        input R,
        input S
 );
 
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr0 (
        .Q(Q[0]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[0]),
        .D1(D1[0]),
-       .D2(D2[0]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr1 (
        .Q(Q[1]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[1]),
        .D1(D1[1]),
-       .D2(D2[1]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr2 (
        .Q(Q[2]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[2]),
        .D1(D1[2]),
-       .D2(D2[2]),
        .R(R),
        .S(S)
 );
-ODDR #(
-       .DDR_CLK_EDGE(DDR_CLK_EDGE),
+ODDR2 #(
+       .DDR_ALIGNMENT(DDR_ALIGNMENT),
        .INIT(INIT),
        .SRTYPE(SRTYPE)
 ) oddr3 (
        .Q(Q[3]),
-       .C(C),
+       .C0(C0),
+       .C1(C1),
        .CE(CE),
+       .D0(D0[3]),
        .D1(D1[3]),
-       .D2(D2[3]),
        .R(R),
        .S(S)
 );
diff --git a/milkymist-core/cores/hpdmc_ddr32/rtl/virtex4/hpdmc_ddrio.v b/milkymist-core/cores/hpdmc_ddr32/rtl/virtex4/hpdmc_ddrio.v
new file mode 100644 (file)
index 0000000..13597e6
--- /dev/null
@@ -0,0 +1,111 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ *
+ * This program is free and excepted software; you can use it, redistribute it
+ * and/or modify it under the terms of the Exception General Public License as
+ * published by the Exception License Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+ * FOR A PARTICULAR PURPOSE. See the Exception General Public License for more
+ * details.
+ *
+ * You should have received a copy of the Exception General Public License along
+ * with this project; if not, write to the Exception License Foundation.
+ */
+
+module hpdmc_ddrio(
+       input sys_clk,
+       input sys_clk_n,
+       input dqs_clk,
+       
+       input direction,
+       input [7:0] mo,
+       input [63:0] do,
+       output [63:0] di,
+       
+       output [3:0] sdram_dqm,
+       inout [31:0] sdram_dq,
+       inout [3:0] sdram_dqs,
+       
+       input idelay_rst,
+       input idelay_ce,
+       input idelay_inc
+);
+
+wire [31:0] sdram_data_out;
+assign sdram_dq = direction ? sdram_data_out : 32'hzzzzzzzz;
+assign sdram_dqs = direction ? {4{dqs_clk}} : 4'hz;
+
+hpdmc_oddr4 oddr_dqm(
+       .Q(sdram_dqm),
+       .C(sys_clk),
+       .CE(1'b1),
+       .D1(mo[7:4]),
+       .D2(mo[3:0]),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+hpdmc_oddr32 oddr_dq(
+       .Q(sdram_data_out),
+       .C(sys_clk),
+       .CE(1'b1),
+       .D1(do[63:32]),
+       .D2(do[31:0]),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+wire [31:0] sdram_dq_delayed;
+
+hpdmc_idelay8 dq_delay0 (
+       .i(sdram_dq[7:0]),
+       .o(sdram_dq_delayed[7:0]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay1 (
+       .i(sdram_dq[15:8]),
+       .o(sdram_dq_delayed[15:8]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay2 (
+       .i(sdram_dq[23:16]),
+       .o(sdram_dq_delayed[23:16]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+hpdmc_idelay8 dq_delay3 (
+       .i(sdram_dq[31:24]),
+       .o(sdram_dq_delayed[31:24]),
+       
+       .clk(sys_clk),
+       .rst(idelay_rst),
+       .ce(idelay_ce),
+       .inc(idelay_inc)
+);
+
+hpdmc_iddr32 iddr_dq(
+       .Q1(di[31:0]),
+       .Q2(di[63:32]),
+       .C(sys_clk),
+       .CE(1'b1),
+       .D(sdram_dq_delayed),
+       .R(1'b0),
+       .S(1'b0)
+);
+
+endmodule