Fixed timing problem
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Wed, 23 Jun 2010 21:05:57 +0000 (23:05 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Wed, 23 Jun 2010 21:05:57 +0000 (23:05 +0200)
cores/pfpu/rtl/pfpu_fmul.v
cores/tmu2/rtl/tmu2_texcache.v
software/include/hw/pfpu.h

index 6447b5c..ee59f54 100644 (file)
@@ -94,7 +94,6 @@ always @(posedge sys_clk) begin
        r2_mant <= r1_mant;
 end
 
-
 /* Stage 4 */
 reg            r3_zero;
 reg            r3_sign;
@@ -115,18 +114,37 @@ always @(posedge sys_clk) begin
 end
 
 /* Stage 5 */
+reg            r4_zero;
+reg            r4_sign;
+reg [7:0]      r4_expn;
+reg [47:0]     r4_mant;
+
+reg r4_valid;
+
+always @(posedge sys_clk) begin
+       if(alu_rst)
+               r4_valid <= 1'b0;
+       else
+               r4_valid <= r3_valid;
+       r4_zero <= r3_zero;
+       r4_sign <= r3_sign;
+       r4_expn <= r3_expn;
+       r4_mant <= r3_mant;
+end
+
+/* Stage 6 */
 always @(posedge sys_clk) begin
        if(alu_rst)
                valid_o <= 1'b0;
        else
-               valid_o <= r3_valid;
-       if(r3_zero)
+               valid_o <= r4_valid;
+       if(r4_zero)
                r <= {1'bx, 8'd0, 23'bx};
        else begin
-               if(~r3_mant[47])
-                       r <= {r3_sign, r3_expn,      r3_mant[45:23]};
+               if(~r4_mant[47])
+                       r <= {r4_sign, r4_expn,      r4_mant[45:23]};
                else
-                       r <= {r3_sign, r3_expn+8'd1, r3_mant[46:24]};
+                       r <= {r4_sign, r4_expn+8'd1, r4_mant[46:24]};
        end
 end
 
index ab6722f..d8fe8ec 100644 (file)
@@ -228,7 +228,6 @@ wire hit_b = ignore_b_2 | (valid_b & (tag_b == tadrb8_2[fml_depth-1:cache_depth]
 wire hit_c = ignore_c_2 | (valid_c & (tag_c == tadrc8_2[fml_depth-1:cache_depth]));
 wire hit_d = ignore_d_2 | (valid_d & (tag_d == tadrd8_2[fml_depth-1:cache_depth]));
 
-`define VERIFY_TEXCACHE
 `ifdef VERIFY_TEXCACHE
 integer x, y;
 reg [15:0] expected;
index 441522b..954b9b9 100644 (file)
@@ -58,7 +58,7 @@
 
 #define PFPU_LATENCY_FADD      (4)
 #define PFPU_LATENCY_FSUB      (4)
-#define PFPU_LATENCY_FMUL      (6)
+#define PFPU_LATENCY_FMUL      (7)
 #define PFPU_LATENCY_FABS      (2)
 #define PFPU_LATENCY_F2I       (2)
 #define PFPU_LATENCY_I2F       (3)