`define CFG_SIGN_EXTEND_ENABLED
`define CFG_MC_DIVIDE_ENABLED
-// Caches disabled
+`define CFG_ICACHE_ENABLED
+`define CFG_ICACHE_ASSOCIATIVITY 2
+`define CFG_ICACHE_SETS 256
+`define CFG_ICACHE_BYTES_PER_LINE 16
+`define CFG_ICACHE_BASE_ADDRESS 32'h0
+`define CFG_ICACHE_LIMIT 32'h7fffffff
+
+//`define CFG_DCACHE_ENABLED
+`define CFG_DCACHE_ASSOCIATIVITY 2
+`define CFG_DCACHE_SETS 512
+`define CFG_DCACHE_BYTES_PER_LINE 16
+`define CFG_DCACHE_BASE_ADDRESS 32'h0
+`define CFG_DCACHE_LIMIT 32'h7fffffff
+
//
// End of common configuration options
.D_RTY_I(1'b0)
);
-`ifdef HEAVY_DEBUG
-always @(posedge sys_clk) begin
- if(cpudbus_cyc & cpudbus_stb) begin
- $display("DBUS: adr:%x we:%b", cpudbus_adr, cpudbus_we);
- end
- if(cpuibus_cyc & cpuibus_stb & cpuibus_ack) begin
- $display("IBUS: adr:%x dat:%x", cpuibus_adr, cpuibus_dat_r);
- end
-end
-`endif
-
//---------------------------------------------------------------------------
// Boot ROM
//---------------------------------------------------------------------------
// BRAM
//---------------------------------------------------------------------------
//
-// On this board, we have 32k of SRAM instead of 4k
+// On this board, we have 16k of SRAM instead of 4k
// so that we have space for loading some programs.
//
bram #(
- .adr_width(15)
+ .adr_width(14)
) bram (
.sys_clk(sys_clk),
.sys_rst(sys_rst),
puts("This is the Milkymist BIOS debug shell.");
puts("It is used for system development and maintainance, and not");
puts("for regular operation.\n");
- puts("Available commands :");
+ puts("Available commands:");
puts("plltest - print status of the SDRAM clocking PLLs");
puts("memtest - extended SDRAM test");
puts("calibrate - run DDR SDRAM calibration tool");
#ifndef __VERSION_H
#define __VERSION_H
-#define VERSION "0.1"
+#define VERSION "0.1.1"
#endif /* __VERSION_H */