FIFO cleanup
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Fri, 18 Jun 2010 15:02:08 +0000 (17:02 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Fri, 18 Jun 2010 15:02:08 +0000 (17:02 +0200)
14 files changed:
boards/milkymist-one/sources.mak
boards/xilinx-ml401/sources.mak
cores/ac97/rtl/ac97_asfifo.v [deleted file]
cores/ac97/rtl/ac97_graycounter.v [deleted file]
cores/ac97/rtl/ac97_transceiver.v
cores/asfifo/rtl/asfifo.v [new file with mode: 0644]
cores/asfifo/rtl/asfifo_graycounter.v [new file with mode: 0644]
cores/minimac/rtl/minimac_asfifo.v [deleted file]
cores/minimac/rtl/minimac_graycounter.v [deleted file]
cores/minimac/rtl/minimac_rxfifo.v
cores/minimac/rtl/minimac_txfifo.v
cores/vgafb/rtl/vgafb.v
cores/vgafb/rtl/vgafb_asfifo.v [deleted file]
cores/vgafb/rtl/vgafb_graycounter.v [deleted file]

index 7ce4713..20d81aa 100644 (file)
@@ -1,5 +1,6 @@
 BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v) $(BOARD_DIR)/../../gen_capabilities.v
 
+ASFIFO_SRC=$(wildcard $(CORES_DIR)/asfifo/rtl/*.v)
 CONBUS_SRC=$(wildcard $(CORES_DIR)/conbus/rtl/*.v)
 LM32_SRC=                                              \
        $(CORES_DIR)/lm32/rtl/lm32_cpu.v                \
@@ -25,8 +26,6 @@ UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
 SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/spartan6/*.v)
 VGAFB_SRC=                                             \
-       $(CORES_DIR)/vgafb/rtl/vgafb_graycounter.v      \
-       $(CORES_DIR)/vgafb/rtl/vgafb_asfifo.v           \
        $(CORES_DIR)/vgafb/rtl/vgafb_pixelfeed.v        \
        $(CORES_DIR)/vgafb/rtl/vgafb_ctlif.v            \
        $(CORES_DIR)/vgafb/rtl/vgafb_fifo64to16.v       \
@@ -62,4 +61,4 @@ TMU_SRC=                                              \
 ETHERNET_SRC=$(wildcard $(CORES_DIR)/minimac/rtl/*.v)
 FMLMETER_SRC=$(wildcard $(CORES_DIR)/fmlmeter/rtl/*.v)
 
-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
+CORES_SRC=$(ASFIFO_SRC) $(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
index fce8739..b4b0415 100644 (file)
@@ -1,5 +1,6 @@
 BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v) $(BOARD_DIR)/../../gen_capabilities.v
 
+ASFIFO_SRC=$(wildcard $(CORES_DIR)/asfifo/rtl/*.v)
 CONBUS_SRC=$(wildcard $(CORES_DIR)/conbus/rtl/*.v)
 LM32_SRC=                                              \
        $(CORES_DIR)/lm32/rtl/lm32_cpu.v                \
@@ -26,8 +27,6 @@ SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 ACEUSB_SRC=$(wildcard $(CORES_DIR)/aceusb/rtl/*.v)
 HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/virtex4/*.v)
 VGAFB_SRC=                                             \
-       $(CORES_DIR)/vgafb/rtl/vgafb_graycounter.v      \
-       $(CORES_DIR)/vgafb/rtl/vgafb_asfifo.v           \
        $(CORES_DIR)/vgafb/rtl/vgafb_pixelfeed.v        \
        $(CORES_DIR)/vgafb/rtl/vgafb_ctlif.v            \
        $(CORES_DIR)/vgafb/rtl/vgafb_fifo64to16.v       \
@@ -64,4 +63,4 @@ PS2_SRC=$(wildcard $(CORES_DIR)/ps2/rtl/*.v)
 ETHERNET_SRC=$(wildcard $(CORES_DIR)/minimac/rtl/*.v)
 FMLMETER_SRC=$(wildcard $(CORES_DIR)/fmlmeter/rtl/*.v)
 
-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(ACEUSB_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(PS2_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
+CORES_SRC=$(ASFIFO_SRC) $(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(ACEUSB_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(PS2_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
diff --git a/cores/ac97/rtl/ac97_asfifo.v b/cores/ac97/rtl/ac97_asfifo.v
deleted file mode 100644 (file)
index 4a10588..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-//==========================================
-// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-// Notes    : This implementation is based on the article 
-//            'Asynchronous FIFO in Virtex-II FPGAs'
-//            writen by Peter Alfke. This TechXclusive 
-//            article can be downloaded from the
-//            Xilinx website. It has some minor modifications.
-//=========================================
-
-`timescale 1ns / 1ps
-
-module ac97_asfifo
-  #(parameter    DATA_WIDTH    = 8,
-                 ADDRESS_WIDTH = 4,
-                 FIFO_DEPTH    = (1 << ADDRESS_WIDTH))
-     //Reading port
-    (output wire [DATA_WIDTH-1:0]        Data_out, 
-     output reg                          Empty_out,
-     input wire                          ReadEn_in,
-     input wire                          RClk,        
-     //Writing port.    
-     input wire  [DATA_WIDTH-1:0]        Data_in,  
-     output reg                          Full_out,
-     input wire                          WriteEn_in,
-     input wire                          WClk,
-     
-     input wire                          Clear_in);
-
-    /////Internal connections & variables//////
-    reg   [DATA_WIDTH-1:0]              Mem [FIFO_DEPTH-1:0];
-    wire  [ADDRESS_WIDTH-1:0]           pNextWordToWrite, pNextWordToRead;
-    wire                                EqualAddresses;
-    wire                                NextWriteAddressEn, NextReadAddressEn;
-    wire                                Set_Status, Rst_Status;
-    reg                                 Status;
-    wire                                PresetFull, PresetEmpty;
-    
-    //////////////Code///////////////
-    //Data ports logic:
-    //(Uses a dual-port RAM).
-    //'Data_out' logic:
-    assign  Data_out = Mem[pNextWordToRead];
-//    always @ (posedge RClk)
-//        if (!PresetEmpty)
-//            Data_out <= Mem[pNextWordToRead];
-//        if (ReadEn_in & !Empty_out)
-            
-    //'Data_in' logic:
-    always @ (posedge WClk)
-        if (WriteEn_in & !Full_out)
-            Mem[pNextWordToWrite] <= Data_in;
-
-    //Fifo addresses support logic: 
-    //'Next Addresses' enable logic:
-    assign NextWriteAddressEn = WriteEn_in & ~Full_out;
-    assign NextReadAddressEn  = ReadEn_in  & ~Empty_out;
-           
-    //Addreses (Gray counters) logic:
-    ac97_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pWr (
-        .GrayCount_out(pNextWordToWrite),
-        .Enable_in(NextWriteAddressEn),
-        .Clear_in(Clear_in),
-        
-        .Clk(WClk)
-       );
-       
-    ac97_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pRd (
-        .GrayCount_out(pNextWordToRead),
-        .Enable_in(NextReadAddressEn),
-        .Clear_in(Clear_in),
-        .Clk(RClk)
-       );
-     
-
-    //'EqualAddresses' logic:
-    assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
-
-    //'Quadrant selectors' logic:
-    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
-                            
-    assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
-                         
-    //'Status' latch logic:
-    always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
-        if (Rst_Status | Clear_in)
-            Status = 0;  //Going 'Empty'.
-        else if (Set_Status)
-            Status = 1;  //Going 'Full'.
-            
-    //'Full_out' logic for the writing port:
-    assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
-    
-    always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetFull)
-            Full_out <= 1;
-        else
-            Full_out <= 0;
-            
-    //'Empty_out' logic for the reading port:
-    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
-    
-    always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetEmpty)
-            Empty_out <= 1;
-        else
-            Empty_out <= 0;
-
-endmodule
diff --git a/cores/ac97/rtl/ac97_graycounter.v b/cores/ac97/rtl/ac97_graycounter.v
deleted file mode 100644 (file)
index 2d9dbd0..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-//==========================================
-// Function : Code Gray counter.
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-//=======================================
-
-`timescale 1ns/1ps
-
-module ac97_graycounter
-   #(parameter   COUNTER_WIDTH = 2)
-   
-    (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output.
-    
-     input wire                         Enable_in,  //Count enable.
-     input wire                         Clear_in,   //Count reset.
-    
-     input wire                         Clk);
-
-    /////////Internal connections & variables///////
-    reg    [COUNTER_WIDTH-1:0]         BinaryCount;
-
-    /////////Code///////////////////////
-    
-    always @ (posedge Clk)
-        if (Clear_in) begin
-            BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;  //Gray count begins @ '1' with
-            GrayCount_out <= {COUNTER_WIDTH{1'b 0}};      // first 'Enable_in'.
-        end
-        else if (Enable_in) begin
-            BinaryCount   <= BinaryCount + 1;
-            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
-                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
-        end
-
-endmodule
index 8db8e19..9e0a59b 100644 (file)
@@ -47,21 +47,21 @@ reg ac97_syncfb_r;
 always @(negedge ac97_clk) ac97_syncfb_r <= ac97_sync;
 
 wire up_empty;
-ac97_asfifo #(
-       .DATA_WIDTH(2),
-       .ADDRESS_WIDTH(6)
+asfifo #(
+       .data_width(2),
+       .address_width(6)
 ) up_fifo (
-       .Data_out({up_sync, up_data}),
-       .Empty_out(up_empty),
-       .ReadEn_in(up_ack),
-       .RClk(sys_clk),
+       .data_out({up_sync, up_data}),
+       .empty(up_empty),
+       .read_en(up_ack),
+       .clk_read(sys_clk),
        
-       .Data_in({ac97_syncfb_r, ac97_sin_r}),
-       .Full_out(),
-       .WriteEn_in(1'b1),
-       .WClk(~ac97_clk),
+       .data_in({ac97_syncfb_r, ac97_sin_r}),
+       .full(),
+       .write_en(1'b1),
+       .clk_write(~ac97_clk),
        
-       .Clear_in(sys_rst)
+       .rst(sys_rst)
 );
 assign up_stb = ~up_empty;
 
@@ -85,21 +85,21 @@ always @(negedge ac97_rst_n, posedge ac97_clk) begin
 end
 
 wire down_full;
-ac97_asfifo #(
-       .DATA_WIDTH(2),
-       .ADDRESS_WIDTH(6)
+asfifo #(
+       .data_width(2),
+       .address_width(6)
 ) down_fifo (
-       .Data_out({ac97_sync_r, ac97_sout_r}),
-       .Empty_out(),
-       .ReadEn_in(1'b1),
-       .RClk(ac97_clk),
+       .data_out({ac97_sync_r, ac97_sout_r}),
+       .empty(),
+       .read_en(1'b1),
+       .clk_read(ac97_clk),
        
-       .Data_in({down_sync, down_data}),
-       .Full_out(down_full),
-       .WriteEn_in(down_stb),
-       .WClk(sys_clk),
-       
-       .Clear_in(sys_rst)
+       .data_in({down_sync, down_data}),
+       .full(down_full),
+       .write_en(down_stb),
+       .clk_write(sys_clk),
+
+       .rst(sys_rst)
 );
 assign down_ready = ~down_full;
 
diff --git a/cores/asfifo/rtl/asfifo.v b/cores/asfifo/rtl/asfifo.v
new file mode 100644 (file)
index 0000000..004bfd7
--- /dev/null
@@ -0,0 +1,115 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is based on "Asynchronous FIFO" by Alex Claros F.,
+ * itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
+ * by Peter Alfke.
+ */
+
+module asfifo #(
+       parameter data_width = 8,
+       parameter address_width = 4,
+       parameter fifo_depth = (1 << address_width)
+) (
+       /* Read port */
+       output [data_width-1:0] data_out,
+       output reg empty,
+       input read_en,
+       input clk_read,
+       
+       /* Write port */
+       input [data_width-1:0] data_in,
+       output reg full,
+       input write_en,
+       input clk_write,
+       
+       /* Asynchronous reset */
+       input rst
+);
+
+reg [data_width-1:0] mem[fifo_depth-1:0];
+wire [address_width-1:0] write_index, read_index;
+wire equal_addresses;
+wire write_en_safe, read_en_safe;
+wire set_status, clear_status;
+reg status;
+wire preset_full, preset_empty;
+
+assign data_out = mem[read_index];
+
+always @(posedge clk_write) begin
+       if (write_en & !full)
+               mem[write_index] <= data_in;
+end
+
+assign write_en_safe = write_en & ~full;
+assign read_en_safe = read_en & ~empty;
+
+asfifo_graycounter #(
+       .width(address_width)
+) counter_write (
+       .gray_count(write_index),
+       .ce(write_en_safe),
+       .rst(rst),
+       .clk(clk_write)
+);
+
+asfifo_graycounter #(
+       .width(address_width)
+) counter_read (
+       .gray_count(read_index),
+       .ce(read_en_safe),
+       .rst(rst),
+       .clk(clk_read)
+);
+
+assign equal_addresses = (write_index == read_index);
+
+assign set_status = (write_index[address_width-2] ~^ read_index[address_width-1]) &
+       (write_index[address_width-1] ^ read_index[address_width-2]);
+
+assign clear_status = ((write_index[address_width-2] ^ read_index[address_width-1]) &
+       (write_index[address_width-1] ~^ read_index[address_width-2]))
+       | rst;
+
+always @(posedge clear_status, posedge set_status) begin
+       if(clear_status)
+               status <= 1'b0;
+       else
+               status <= 1'b1;
+end
+
+assign preset_full = status & equal_addresses;
+
+always @(posedge clk_write, posedge preset_full) begin
+       if(preset_full)
+               full <= 1'b1;
+       else
+               full <= 1'b0;
+end
+
+assign preset_empty = ~status & equal_addresses;
+
+always @(posedge clk_read, posedge preset_empty) begin
+       if(preset_empty)
+               empty <= 1'b1;
+       else
+               empty <= 1'b0;
+end
+
+endmodule
diff --git a/cores/asfifo/rtl/asfifo_graycounter.v b/cores/asfifo/rtl/asfifo_graycounter.v
new file mode 100644 (file)
index 0000000..7e7a3af
--- /dev/null
@@ -0,0 +1,46 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/*
+ * This file is based on "Asynchronous FIFO" by Alex Claros F.,
+ * itself based on the article "Asynchronous FIFO in Virtex-II FPGAs"
+ * by Peter Alfke.
+ */
+
+module asfifo_graycounter #(
+       parameter width = 2
+) (
+       output reg [width-1:0] gray_count,
+       input ce,
+       input rst,
+       input clk
+);
+
+reg [width-1:0] binary_count;
+
+always @(posedge clk, posedge rst) begin
+       if(rst) begin
+               binary_count <= {width{1'b0}} + 1;
+               gray_count <= {width{1'b0}};
+       end else if(ce) begin
+               binary_count <= binary_count + 1;
+               gray_count <= {binary_count[width-1],
+                               binary_count[width-2:0] ^ binary_count[width-1:1]};
+       end
+end
+
+endmodule
diff --git a/cores/minimac/rtl/minimac_asfifo.v b/cores/minimac/rtl/minimac_asfifo.v
deleted file mode 100644 (file)
index 3d6785c..0000000
+++ /dev/null
@@ -1,114 +0,0 @@
-//==========================================
-// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-// Notes    : This implementation is based on the article 
-//            'Asynchronous FIFO in Virtex-II FPGAs'
-//            writen by Peter Alfke. This TechXclusive 
-//            article can be downloaded from the
-//            Xilinx website. It has some minor modifications.
-//=========================================
-
-module minimac_asfifo
-  #(parameter    DATA_WIDTH    = 8,
-                 ADDRESS_WIDTH = 4,
-                 FIFO_DEPTH    = (1 << ADDRESS_WIDTH))
-     //Reading port
-    (output wire [DATA_WIDTH-1:0]        Data_out, 
-     output reg                          Empty_out,
-     input wire                          ReadEn_in,
-     input wire                          RClk,        
-     //Writing port.    
-     input wire  [DATA_WIDTH-1:0]        Data_in,  
-     output reg                          Full_out,
-     input wire                          WriteEn_in,
-     input wire                          WClk,
-     
-     input wire                          Clear_in);
-
-    /////Internal connections & variables//////
-    reg   [DATA_WIDTH-1:0]              Mem [FIFO_DEPTH-1:0];
-    wire  [ADDRESS_WIDTH-1:0]           pNextWordToWrite, pNextWordToRead;
-    wire                                EqualAddresses;
-    wire                                NextWriteAddressEn, NextReadAddressEn;
-    wire                                Set_Status, Rst_Status;
-    reg                                 Status;
-    wire                                PresetFull, PresetEmpty;
-    
-    //////////////Code///////////////
-    //Data ports logic:
-    //(Uses a dual-port RAM).
-    //'Data_out' logic:
-    assign  Data_out = Mem[pNextWordToRead];
-//    always @ (posedge RClk)
-//        if (!PresetEmpty)
-//            Data_out <= Mem[pNextWordToRead];
-//        if (ReadEn_in & !Empty_out)
-            
-    //'Data_in' logic:
-    always @ (posedge WClk)
-        if (WriteEn_in & !Full_out)
-            Mem[pNextWordToWrite] <= Data_in;
-
-    //Fifo addresses support logic: 
-    //'Next Addresses' enable logic:
-    assign NextWriteAddressEn = WriteEn_in & ~Full_out;
-    assign NextReadAddressEn  = ReadEn_in  & ~Empty_out;
-           
-    //Addreses (Gray counters) logic:
-    minimac_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pWr (
-        .GrayCount_out(pNextWordToWrite),
-        .Enable_in(NextWriteAddressEn),
-        .Clear_in(Clear_in),
-        
-        .Clk(WClk)
-       );
-       
-    minimac_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pRd (
-        .GrayCount_out(pNextWordToRead),
-        .Enable_in(NextReadAddressEn),
-        .Clear_in(Clear_in),
-        .Clk(RClk)
-       );
-     
-
-    //'EqualAddresses' logic:
-    assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
-
-    //'Quadrant selectors' logic:
-    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
-                            
-    assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
-                         
-    //'Status' latch logic:
-    always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
-        if (Rst_Status | Clear_in)
-            Status = 0;  //Going 'Empty'.
-        else if (Set_Status)
-            Status = 1;  //Going 'Full'.
-            
-    //'Full_out' logic for the writing port:
-    assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
-    
-    always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetFull)
-            Full_out <= 1;
-        else
-            Full_out <= 0;
-            
-    //'Empty_out' logic for the reading port:
-    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
-    
-    always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetEmpty)
-            Empty_out <= 1;
-        else
-            Empty_out <= 0;
-
-endmodule
diff --git a/cores/minimac/rtl/minimac_graycounter.v b/cores/minimac/rtl/minimac_graycounter.v
deleted file mode 100644 (file)
index fb63d46..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-//==========================================
-// Function : Code Gray counter.
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-//=======================================
-
-`timescale 1ns/1ps
-
-module minimac_graycounter
-   #(parameter   COUNTER_WIDTH = 2)
-   
-    (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output.
-    
-     input wire                         Enable_in,  //Count enable.
-     input wire                         Clear_in,   //Count reset.
-    
-     input wire                         Clk);
-
-    /////////Internal connections & variables///////
-    reg    [COUNTER_WIDTH-1:0]         BinaryCount;
-
-    /////////Code///////////////////////
-    
-    always @ (posedge Clk)
-        if (Clear_in) begin
-            BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;  //Gray count begins @ '1' with
-            GrayCount_out <= {COUNTER_WIDTH{1'b 0}};      // first 'Enable_in'.
-        end
-        else if (Enable_in) begin
-            BinaryCount   <= BinaryCount + 1;
-            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
-                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
-        end
-
-endmodule
index 78f4943..882b97b 100644 (file)
@@ -49,20 +49,21 @@ wire [8:0] fifo_in = {fifo_eof, fifo_hi, fifo_lo};
 reg fifo_we;
 wire full;
 
-minimac_asfifo #(
-       .DATA_WIDTH(9),
-       .ADDRESS_WIDTH(7)
+asfifo #(
+       .data_width(9),
+       .address_width(7)
 ) fifo (
-       .Data_out(fifo_out),
-       .Empty_out(empty),
-       .ReadEn_in(ack),
-       .RClk(sys_clk),
-
-       .Data_in(fifo_in),
-       .Full_out(full),
-       .WriteEn_in(fifo_we),
-       .WClk(phy_rx_clk),
-       .Clear_in(rx_rst)
+       .data_out(fifo_out),
+       .empty(empty),
+       .read_en(ack),
+       .clk_read(sys_clk),
+
+       .data_in(fifo_in),
+       .full(full),
+       .write_en(fifo_we),
+       .clk_write(phy_rx_clk),
+       
+       .rst(rx_rst)
 );
 
 /* we assume f(sys_clk) > f(phy_rx_clk) */
index c1d0206..b4da3db 100644 (file)
@@ -40,20 +40,21 @@ always @(posedge sys_clk) begin
        empty <= empty2;
 end
 
-minimac_asfifo #(
-       .DATA_WIDTH(8),
-       .ADDRESS_WIDTH(7)
+asfifo #(
+       .data_width(8),
+       .address_width(7)
 ) fifo (
-       .Data_out(fifo_out),
-       .Empty_out(fifo_empty),
-       .ReadEn_in(fifo_read),
-       .RClk(phy_tx_clk),
-
-       .Data_in(data),
-       .Full_out(full),
-       .WriteEn_in(stb),
-       .WClk(sys_clk),
-       .Clear_in(tx_rst)
+       .data_out(fifo_out),
+       .empty(fifo_empty),
+       .read_en(fifo_read),
+       .clk_read(phy_tx_clk),
+
+       .data_in(data),
+       .full(full),
+       .write_en(stb),
+       .clk_write(sys_clk),
+
+       .rst(tx_rst)
 );
 
 reg can_tx1;
index 8d58c2d..f4e30e9 100644 (file)
@@ -200,21 +200,21 @@ vgafb_pixelfeed #(
  */
 wire [17:0] fifo_do;
 
-vgafb_asfifo #(
-       .DATA_WIDTH(18),
-       .ADDRESS_WIDTH(6)
+asfifo #(
+       .data_width(18),
+       .address_width(6)
 ) fifo (
-       .Data_out(fifo_do),
-       .Empty_out(),
-       .ReadEn_in(1'b1),
-       .RClk(vga_clk),
+       .data_out(fifo_do),
+       .empty(),
+       .read_en(1'b1),
+       .clk_read(vga_clk),
        
-       .Data_in({vsync_n, hsync_n, pixel}),
-       .Full_out(fifo_full),
-       .WriteEn_in(generate_en),
-       .WClk(sys_clk),
+       .data_in({vsync_n, hsync_n, pixel}),
+       .full(fifo_full),
+       .write_en(generate_en),
+       .clk_write(sys_clk),
        
-       .Clear_in(vga_rst)
+       .rst(vga_rst)
 );
 
 /*
diff --git a/cores/vgafb/rtl/vgafb_asfifo.v b/cores/vgafb/rtl/vgafb_asfifo.v
deleted file mode 100644 (file)
index 26d725e..0000000
+++ /dev/null
@@ -1,122 +0,0 @@
-//==========================================
-// Function : Asynchronous FIFO (w/ 2 asynchronous clocks).
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-// Notes    : This implementation is based on the article 
-//            'Asynchronous FIFO in Virtex-II FPGAs'
-//            writen by Peter Alfke. This TechXclusive 
-//            article can be downloaded from the
-//            Xilinx website. It has some minor modifications.
-//=========================================
-
-`timescale 1ns / 1ps
-
-module vgafb_asfifo
-  #(parameter    DATA_WIDTH    = 8,
-                 ADDRESS_WIDTH = 4,
-                 FIFO_DEPTH    = (1 << ADDRESS_WIDTH))
-     //Reading port
-    (output wire [DATA_WIDTH-1:0]        Data_out, 
-     output reg                          Empty_out,
-     input wire                          ReadEn_in,
-     input wire                          RClk,        
-     //Writing port.    
-     input wire  [DATA_WIDTH-1:0]        Data_in,  
-     output reg                          Full_out,
-     input wire                          WriteEn_in,
-     input wire                          WClk,
-     
-     input wire                          Clear_in);
-
-    /////Internal connections & variables//////
-    reg   [DATA_WIDTH-1:0]              Mem [FIFO_DEPTH-1:0];
-    wire  [ADDRESS_WIDTH-1:0]           pNextWordToWrite, pNextWordToRead;
-    wire                                EqualAddresses;
-    wire                                NextWriteAddressEn, NextReadAddressEn;
-    wire                                Set_Status, Rst_Status;
-    reg                                 Status;
-    wire                                PresetFull, PresetEmpty;
-    
-    //////////////Code///////////////
-    //Data ports logic:
-    //(Uses a dual-port RAM).
-    //'Data_out' logic:
-    assign  Data_out = Mem[pNextWordToRead];
-//    always @ (posedge RClk)
-//        if (!PresetEmpty)
-//            Data_out <= Mem[pNextWordToRead];
-//        if (ReadEn_in & !Empty_out)
-            
-    //'Data_in' logic:
-    always @ (posedge WClk)
-        if (WriteEn_in & !Full_out)
-            Mem[pNextWordToWrite] <= Data_in;
-
-    //Fifo addresses support logic: 
-    //'Next Addresses' enable logic:
-    assign NextWriteAddressEn = WriteEn_in & ~Full_out;
-    assign NextReadAddressEn  = ReadEn_in  & ~Empty_out;
-           
-    //Addreses (Gray counters) logic:
-    vgafb_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pWr (
-        .GrayCount_out(pNextWordToWrite),
-        .Enable_in(NextWriteAddressEn),
-        .Clear_in(Clear_in),
-        
-        .Clk(WClk)
-       );
-       
-    vgafb_graycounter #(
-               .COUNTER_WIDTH( ADDRESS_WIDTH )
-    ) GrayCounter_pRd (
-        .GrayCount_out(pNextWordToRead),
-        .Enable_in(NextReadAddressEn),
-        .Clear_in(Clear_in),
-        .Clk(RClk)
-       );
-     
-
-    //'EqualAddresses' logic:
-    assign EqualAddresses = (pNextWordToWrite == pNextWordToRead);
-
-    //'Quadrant selectors' logic:
-    assign Set_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ~^ pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ^  pNextWordToRead[ADDRESS_WIDTH-2]);
-                            
-    assign Rst_Status = (pNextWordToWrite[ADDRESS_WIDTH-2] ^  pNextWordToRead[ADDRESS_WIDTH-1]) &
-                         (pNextWordToWrite[ADDRESS_WIDTH-1] ~^ pNextWordToRead[ADDRESS_WIDTH-2]);
-                         
-    //'Status' latch logic:
-    /*always @ (Set_Status, Rst_Status, Clear_in) //D Latch w/ Asynchronous Clear & Preset.
-        if (Rst_Status | Clear_in)
-            Status = 0;  //Going 'Empty'.
-        else if (Set_Status)
-            Status = 1;  //Going 'Full'.*/
-   wire clear_status = Rst_Status | Clear_in;
-   always @(posedge clear_status, posedge Set_Status)
-      if(clear_status)
-         Status <= 1'b0;
-      else
-         Status <= 1'b1;
-            
-    //'Full_out' logic for the writing port:
-    assign PresetFull = Status & EqualAddresses;  //'Full' Fifo.
-    
-    always @ (posedge WClk, posedge PresetFull) //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetFull)
-            Full_out <= 1;
-        else
-            Full_out <= 0;
-            
-    //'Empty_out' logic for the reading port:
-    assign PresetEmpty = ~Status & EqualAddresses;  //'Empty' Fifo.
-    
-    always @ (posedge RClk, posedge PresetEmpty)  //D Flip-Flop w/ Asynchronous Preset.
-        if (PresetEmpty)
-            Empty_out <= 1;
-        else
-            Empty_out <= 0;
-
-endmodule
diff --git a/cores/vgafb/rtl/vgafb_graycounter.v b/cores/vgafb/rtl/vgafb_graycounter.v
deleted file mode 100644 (file)
index 4844c69..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-//==========================================
-// Function : Code Gray counter.
-// Coder    : Alex Claros F.
-// Date     : 15/May/2005.
-//=======================================
-
-`timescale 1ns/1ps
-
-module vgafb_graycounter
-   #(parameter   COUNTER_WIDTH = 2)
-   
-    (output reg  [COUNTER_WIDTH-1:0]    GrayCount_out,  //'Gray' code count output.
-    
-     input wire                         Enable_in,  //Count enable.
-     input wire                         Clear_in,   //Count reset.
-    
-     input wire                         Clk);
-
-    /////////Internal connections & variables///////
-    reg    [COUNTER_WIDTH-1:0]         BinaryCount;
-
-    /////////Code///////////////////////
-    
-    always @ (posedge Clk)
-        if (Clear_in) begin
-            BinaryCount   <= {COUNTER_WIDTH{1'b 0}} + 1;  //Gray count begins @ '1' with
-            GrayCount_out <= {COUNTER_WIDTH{1'b 0}};      // first 'Enable_in'.
-        end
-        else if (Enable_in) begin
-            BinaryCount   <= BinaryCount + 1;
-            GrayCount_out <= {BinaryCount[COUNTER_WIDTH-1],
-                              BinaryCount[COUNTER_WIDTH-2:0] ^ BinaryCount[COUNTER_WIDTH-1:1]};
-        end
-
-endmodule