16 bit flash support
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Sat, 19 Jun 2010 11:48:15 +0000 (13:48 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Sat, 19 Jun 2010 11:48:15 +0000 (13:48 +0200)
boards/milkymist-one/rtl/system.v
boards/milkymist-one/sources.mak
cores/norflash16/rtl/norflash16.v [new file with mode: 0644]
cores/norflash16/test/Makefile [new file with mode: 0644]
cores/norflash16/test/tb_norflash16.v [new file with mode: 0644]
cores/norflash8/doc/s29gl032n.pdf [deleted file]
cores/norflash8/rtl/norflash8.v [deleted file]
cores/norflash8/test/Makefile [deleted file]
cores/norflash8/test/tb_norflash8.v [deleted file]

index 07557af..5c2895d 100644 (file)
@@ -675,7 +675,7 @@ lm32_top cpu(
 //---------------------------------------------------------------------------
 // Boot ROM
 //---------------------------------------------------------------------------
-norflash8 #(
+norflash16 #(
        .adr_width(24)
 ) norflash (
        .sys_clk(sys_clk),
index 20d81aa..1765130 100644 (file)
@@ -21,7 +21,7 @@ LM32_SRC=                                             \
 FMLARB_SRC=$(wildcard $(CORES_DIR)/fmlarb/rtl/*.v)
 FMLBRG_SRC=$(wildcard $(CORES_DIR)/fmlbrg/rtl/*.v)
 CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v)
-NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash8/rtl/*.v)
+NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash16/rtl/*.v)
 UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
 SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/spartan6/*.v)
diff --git a/cores/norflash16/rtl/norflash16.v b/cores/norflash16/rtl/norflash16.v
new file mode 100644 (file)
index 0000000..1a30d8a
--- /dev/null
@@ -0,0 +1,110 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+module norflash16 #(
+       parameter adr_width = 22,
+       parameter timing = 4'd12
+) (
+       input sys_clk,
+       input sys_rst,
+
+       input [31:0] wb_adr_i,
+       output reg [31:0] wb_dat_o,
+       input wb_stb_i,
+       input wb_cyc_i,
+       output reg wb_ack_o,
+       
+       output [adr_width-1:0] flash_adr,
+       input [15:0] flash_d
+);
+
+reg [adr_width-1-1:0] flash_adr_msb;
+reg flash_adr_lsb;
+
+assign flash_adr = {flash_adr_msb, flash_adr_lsb};
+
+reg load;
+always @(posedge sys_clk) begin
+       /* Use IOB registers to prevent glitches on address lines */
+       if(wb_cyc_i & wb_stb_i) /* register only when needed to reduce EMI */
+               flash_adr_msb <= wb_adr_i[adr_width-1:2];
+       if(load) begin
+               case(flash_adr_lsb)
+                       1'b0: wb_dat_o[31:16] <= flash_d;
+                       1'b1: wb_dat_o[15:0] <= flash_d;
+               endcase
+               flash_adr_lsb <= ~flash_adr_lsb;
+       end
+       if(sys_rst)
+               flash_adr_lsb <= 1'b0;
+end
+
+/*
+ * Timing of the flash chips is typically 110ns.
+ */
+reg [3:0] counter;
+reg counter_en;
+wire counter_done = (counter == timing);
+always @(posedge sys_clk) begin
+       if(sys_rst)
+               counter <= 4'd0;
+       else begin
+               if(counter_en & ~counter_done)
+                       counter <= counter + 4'd1;
+               else
+                       counter <= 4'd0;
+       end
+end
+
+reg [1:0] state;
+reg [1:0] next_state;
+always @(posedge sys_clk) begin
+       if(sys_rst)
+               state <= 1'b0;
+       else
+               state <= next_state;
+end
+
+always @(*) begin
+       next_state = state;
+       counter_en = 1'b0;
+       load = 1'b0;
+       wb_ack_o = 1'b0;
+
+       case(state)
+               2'd0: begin
+                       if(wb_cyc_i & wb_stb_i)
+                               next_state = 2'd1;
+               end
+
+               2'd1: begin
+                       counter_en = 1'b1;
+                       if(counter_done) begin
+                               load = 1'b1;
+                               if(flash_adr_lsb)
+                                       next_state = 2'd2;
+                       end
+               end
+
+               2'd2: begin
+                       wb_ack_o = 1'b1;
+                       next_state = 2'd0;
+               end
+       endcase
+end
+
+endmodule
diff --git a/cores/norflash16/test/Makefile b/cores/norflash16/test/Makefile
new file mode 100644 (file)
index 0000000..a132b44
--- /dev/null
@@ -0,0 +1,17 @@
+SOURCES=tb_norflash16.v $(wildcard ../rtl/*.v)
+
+all: tb_norflash16
+
+isim: tb_norflash16
+       ./tb_norflash16
+
+cversim: $(SOURCES)
+       cver $(SOURCES)
+
+clean:
+       rm -f tb_norflash16 verilog.log norflash16.vcd
+
+tb_norflash16: $(SOURCES)
+       iverilog -o tb_norflash16 $(SOURCES)
+
+.PHONY: clean sim cversim
diff --git a/cores/norflash16/test/tb_norflash16.v b/cores/norflash16/test/tb_norflash16.v
new file mode 100644 (file)
index 0000000..5a74431
--- /dev/null
@@ -0,0 +1,106 @@
+/*
+ * Milkymist VJ SoC
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+`timescale 1ns / 1ps
+
+module tb_norflash16();
+
+reg sys_clk;
+reg sys_rst;
+
+reg [31:0] wb_adr_i;
+wire [31:0] wb_dat_o;
+reg wb_cyc_i;
+reg wb_stb_i;
+wire wb_ack_o;
+
+wire [6:0] aceusb_a;
+wire [15:0] aceusb_d;
+
+wire [21:0] flash_adr;
+reg [15:0] flash_d;
+
+always @(flash_adr) #110 flash_d <= flash_adr[15:0] + 8'd1;
+
+norflash16 dut(
+       .sys_clk(sys_clk),
+       .sys_rst(sys_rst),
+
+       .wb_adr_i(wb_adr_i),
+       .wb_dat_o(wb_dat_o),
+       .wb_cyc_i(wb_cyc_i),
+       .wb_stb_i(wb_stb_i),
+       .wb_ack_o(wb_ack_o),
+
+       .flash_adr(flash_adr),
+       .flash_d(flash_d)
+);
+
+task wbread;
+       input [31:0] address;
+       integer i;
+       begin
+               wb_adr_i = address;
+               wb_cyc_i = 1'b1;
+               wb_stb_i = 1'b1;
+               
+               i = 1;
+               while(~wb_ack_o) begin
+                       #5 sys_clk = 1'b1;
+                       #5 sys_clk = 1'b0;
+                       i = i + 1;
+               end
+               
+               $display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
+               
+               /* Let the core release its ack */
+               #5 sys_clk = 1'b1;
+               #5 sys_clk = 1'b0;
+               
+               wb_cyc_i = 1'b0;
+               wb_stb_i = 1'b0;
+       end
+endtask
+
+initial begin
+       sys_rst = 1'b1;
+       sys_clk = 1'b0;
+       
+       wb_adr_i = 32'h00000000;
+       wb_cyc_i = 1'b0;
+       wb_stb_i = 1'b0;
+
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       
+       sys_rst = 1'b0;
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       
+       wbread(32'h00000020);
+       wbread(32'h00000010);
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       #5 sys_clk = 1'b1;
+       #5 sys_clk = 1'b0;
+       wbread(32'h00000040);
+       
+       $finish;
+end
+
+endmodule
+
diff --git a/cores/norflash8/doc/s29gl032n.pdf b/cores/norflash8/doc/s29gl032n.pdf
deleted file mode 100644 (file)
index a97dc1b..0000000
Binary files a/cores/norflash8/doc/s29gl032n.pdf and /dev/null differ
diff --git a/cores/norflash8/rtl/norflash8.v b/cores/norflash8/rtl/norflash8.v
deleted file mode 100644 (file)
index 7dc387c..0000000
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module norflash8 #(
-       parameter adr_width = 22,
-       parameter timing = 4'd12,
-       parameter swapbytes = 1'b0
-) (
-       input sys_clk,
-       input sys_rst,
-
-       input [31:0] wb_adr_i,
-       output reg [31:0] wb_dat_o,
-       input wb_stb_i,
-       input wb_cyc_i,
-       output reg wb_ack_o,
-       
-       output [adr_width-1:0] flash_adr,
-       input [7:0] flash_d
-);
-
-reg [adr_width-1-2:0] flash_adr_msb;
-reg [1:0] flash_adr_lsb;
-
-assign flash_adr = {flash_adr_msb, flash_adr_lsb[1], swapbytes ^ flash_adr_lsb[0]};
-
-reg load;
-reg reset_flash_adr_lsb;
-always @(posedge sys_clk) begin
-       /* Use IOB registers to prevent glitches on address lines */
-       if(wb_cyc_i & wb_stb_i) /* register only when needed to reduce EMI */
-               flash_adr_msb <= wb_adr_i[adr_width-1:2];
-       if(load) begin
-               case(flash_adr_lsb[1:0])
-                       2'b00: wb_dat_o[31:24] <= flash_d;
-                       2'b01: wb_dat_o[23:16] <= flash_d;
-                       2'b10: wb_dat_o[15:8] <= flash_d;
-                       2'b11: wb_dat_o[7:0] <= flash_d;
-               endcase
-               flash_adr_lsb <= flash_adr_lsb + 2'd1;
-       end
-       if(reset_flash_adr_lsb)
-               flash_adr_lsb <= 2'd0;
-end
-
-/*
- * Timing of the flash chips is typically 110ns.
- */
-reg [3:0] counter;
-reg counter_en;
-wire counter_done = (counter == timing);
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               counter <= 4'd0;
-       else begin
-               if(counter_en & ~counter_done)
-                       counter <= counter + 4'd1;
-               else
-                       counter <= 4'd0;
-       end
-end
-
-reg [1:0] state;
-reg [1:0] next_state;
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               state <= 1'b0;
-       else
-               state <= next_state;
-end
-
-always @(*) begin
-       next_state = state;
-       reset_flash_adr_lsb = 1'b0;
-       counter_en = 1'b0;
-       load = 1'b0;
-       wb_ack_o = 1'b0;
-
-       case(state)
-               2'd0: begin
-                       reset_flash_adr_lsb = 1'b1;
-                       if(wb_cyc_i & wb_stb_i)
-                               next_state = 2'd1;
-               end
-
-               2'd1: begin
-                       counter_en = 1'b1;
-                       if(counter_done) begin
-                               load = 1'b1;
-                               if(flash_adr_lsb == 2'b11)
-                                       next_state = 2'd2;
-                       end
-               end
-
-               2'd2: begin
-                       wb_ack_o = 1'b1;
-                       next_state = 2'd0;
-               end
-       endcase
-end
-
-endmodule
diff --git a/cores/norflash8/test/Makefile b/cores/norflash8/test/Makefile
deleted file mode 100644 (file)
index 810e164..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-SOURCES=tb_norflash8.v $(wildcard ../rtl/*.v)
-
-all: tb_norflash8
-
-isim: tb_norflash8
-       ./tb_norflash8
-
-cversim: $(SOURCES)
-       cver $(SOURCES)
-
-clean:
-       rm -f tb_norflash8 verilog.log norflash8.vcd
-
-tb_norflash8: $(SOURCES)
-       iverilog -o tb_norflash8 $(SOURCES)
-
-.PHONY: clean sim cversim
diff --git a/cores/norflash8/test/tb_norflash8.v b/cores/norflash8/test/tb_norflash8.v
deleted file mode 100644 (file)
index 2f3a0d2..0000000
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`timescale 1ns / 1ps
-
-module tb_norflash8();
-
-reg sys_clk;
-reg sys_rst;
-
-reg [31:0] wb_adr_i;
-wire [31:0] wb_dat_o;
-reg wb_cyc_i;
-reg wb_stb_i;
-wire wb_ack_o;
-
-wire [6:0] aceusb_a;
-wire [15:0] aceusb_d;
-
-wire [21:0] flash_adr;
-reg [7:0] flash_d;
-
-always @(flash_adr) #110 flash_d <= flash_adr[7:0] + 8'd1;
-
-norflash8 dut(
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .wb_adr_i(wb_adr_i),
-       .wb_dat_o(wb_dat_o),
-       .wb_cyc_i(wb_cyc_i),
-       .wb_stb_i(wb_stb_i),
-       .wb_ack_o(wb_ack_o),
-
-       .flash_adr(flash_adr),
-       .flash_d(flash_d)
-);
-
-task wbread;
-       input [31:0] address;
-       integer i;
-       begin
-               wb_adr_i = address;
-               wb_cyc_i = 1'b1;
-               wb_stb_i = 1'b1;
-               
-               i = 1;
-               while(~wb_ack_o) begin
-                       #5 sys_clk = 1'b1;
-                       #5 sys_clk = 1'b0;
-                       i = i + 1;
-               end
-               
-               $display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
-               
-               /* Let the core release its ack */
-               #5 sys_clk = 1'b1;
-               #5 sys_clk = 1'b0;
-               
-               wb_cyc_i = 1'b0;
-               wb_stb_i = 1'b0;
-       end
-endtask
-
-initial begin
-       sys_rst = 1'b1;
-       sys_clk = 1'b0;
-       
-       wb_adr_i = 32'h00000000;
-       wb_cyc_i = 1'b0;
-       wb_stb_i = 1'b0;
-
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       
-       sys_rst = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       
-       wbread(32'h00000020);
-       wbread(32'h00000010);
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       wbread(32'h00000040);
-       
-       $finish;
-end
-
-endmodule
-