change includes to use new csr base address master
authorMichael Walle <michael@walle.cc>
Wed, 7 Jul 2010 22:38:52 +0000 (00:38 +0200)
committerMichael Walle <michael@walle.cc>
Wed, 7 Jul 2010 22:38:52 +0000 (00:38 +0200)
13 files changed:
software/include/hw/ac97.h
software/include/hw/bt656cap.h
software/include/hw/fmlmeter.h
software/include/hw/hpdmc.h
software/include/hw/midi.h
software/include/hw/minimac.h
software/include/hw/pfpu.h
software/include/hw/rc5.h
software/include/hw/sysctl.h
software/include/hw/tags [new file with mode: 0644]
software/include/hw/tmu.h
software/include/hw/uart.h
software/include/hw/vga.h

index 6e348e8..fa5035e 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_AC97_CRCTL         MMPTR(0x80004000)
+#define CSR_AC97_CRCTL         MMPTR(0xe0004000)
 
 #define AC97_CRCTL_RQEN                (0x01)
 #define AC97_CRCTL_WRITE       (0x02)
 
-#define CSR_AC97_CRADDR                MMPTR(0x80004004)
-#define CSR_AC97_CRDATAOUT     MMPTR(0x80004008)
-#define CSR_AC97_CRDATAIN      MMPTR(0x8000400C)
+#define CSR_AC97_CRADDR                MMPTR(0xe0004004)
+#define CSR_AC97_CRDATAOUT     MMPTR(0xe0004008)
+#define CSR_AC97_CRDATAIN      MMPTR(0xe000400C)
 
-#define CSR_AC97_DCTL          MMPTR(0x80004010)
-#define CSR_AC97_DADDRESS      MMPTR(0x80004014)
-#define CSR_AC97_DREMAINING    MMPTR(0x80004018)
+#define CSR_AC97_DCTL          MMPTR(0xe0004010)
+#define CSR_AC97_DADDRESS      MMPTR(0xe0004014)
+#define CSR_AC97_DREMAINING    MMPTR(0xe0004018)
 
-#define CSR_AC97_UCTL          MMPTR(0x80004020)
-#define CSR_AC97_UADDRESS      MMPTR(0x80004024)
-#define CSR_AC97_UREMAINING    MMPTR(0x80004028)
+#define CSR_AC97_UCTL          MMPTR(0xe0004020)
+#define CSR_AC97_UADDRESS      MMPTR(0xe0004024)
+#define CSR_AC97_UREMAINING    MMPTR(0xe0004028)
 
 #define AC97_SCTL_EN           (0x01)
 
index e2005c9..525f4dc 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_BT656CAP_I2C               MMPTR(0x8000b000)
-#define CSR_BT656CAP_FILTERSTATUS      MMPTR(0x8000b004)
-#define CSR_BT656CAP_BASE              MMPTR(0x8000b008)
-#define CSR_BT656CAP_MAXBURSTS         MMPTR(0x8000b00C)
-#define CSR_BT656CAP_DONEBURSTS                MMPTR(0x8000b010)
+#define CSR_BT656CAP_I2C               MMPTR(0xe000b000)
+#define CSR_BT656CAP_FILTERSTATUS      MMPTR(0xe000b004)
+#define CSR_BT656CAP_BASE              MMPTR(0xe000b008)
+#define CSR_BT656CAP_MAXBURSTS         MMPTR(0xe000b00C)
+#define CSR_BT656CAP_DONEBURSTS                MMPTR(0xe000b010)
 
 #define BT656CAP_I2C_SDAIN             (0x1)
 #define BT656CAP_I2C_SDAOUT            (0x2)
index 1ff3600..83db609 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_FMLMETER_ENABLE    MMPTR(0x8000a000)
+#define CSR_FMLMETER_ENABLE    MMPTR(0xe000a000)
 
 #define FMLMETER_ENABLE                (0x01)
 
-#define CSR_FMLMETER_STBCOUNT  MMPTR(0x8000a004)
-#define CSR_FMLMETER_ACKCOUNT  MMPTR(0x8000a008)
+#define CSR_FMLMETER_STBCOUNT  MMPTR(0xe000a004)
+#define CSR_FMLMETER_ACKCOUNT  MMPTR(0xe000a008)
 
 #endif /* __HW_FMLMETER_H */
index 3288617..d6b63b5 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_HPDMC_SYSTEM       MMPTR(0x80002000)
+#define CSR_HPDMC_SYSTEM       MMPTR(0xe0002000)
 
 #define HPDMC_SYSTEM_BYPASS    (0x01)
 #define HPDMC_SYSTEM_RESET     (0x02)
 #define HPDMC_SYSTEM_CKE       (0x04)
 
-#define CSR_HPDMC_BYPASS       MMPTR(0x80002004)
+#define CSR_HPDMC_BYPASS       MMPTR(0xe0002004)
 
 #define HPDMC_BYPASS_CS                (0x01)
 #define HPDMC_BYPASS_WE                (0x02)
@@ -35,7 +35,7 @@
 #define HPDMC_BYPASS_A_S       (4)
 #define HPDMC_BYPASS_BA_S      (17)
 
-#define CSR_HPDMC_TIMING       MMPTR(0x80002008)
+#define CSR_HPDMC_TIMING       MMPTR(0xe0002008)
 
 #define HPDMC_TIMING_TRP_S     (0)
 #define HPDMC_TIMING_TRCD_S    (3)
@@ -44,7 +44,7 @@
 #define HPDMC_TIMING_TRFC_S    (18)
 #define HPDMC_TIMING_TWR_S     (22)
 
-#define CSR_HPDMC_IODELAY      MMPTR(0x8000200C)
+#define CSR_HPDMC_IODELAY      MMPTR(0xe000200C)
 
 #define HPDMC_IDELAY_RST       (0x01)
 #define HPDMC_IDELAY_CE                (0x02)
index 6faee8d..f6576be 100644 (file)
@@ -20,7 +20,7 @@
 
 #include <hw/common.h>
 
-#define CSR_MIDI_RXTX          MMPTR(0x8000d000)
-#define CSR_MIDI_DIVISOR       MMPTR(0x8000d004)
+#define CSR_MIDI_RXTX          MMPTR(0xe000d000)
+#define CSR_MIDI_DIVISOR       MMPTR(0xe000d004)
 
 #endif /* __HW_MIDI_H */
index 7efa6fa..39c64cd 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_MINIMAC_SETUP              MMPTR(0x80009000)
+#define CSR_MINIMAC_SETUP              MMPTR(0xe0009000)
 
 #define MINIMAC_SETUP_RXRST            (0x1)
 #define MINIMAC_SETUP_TXRST            (0x2)
 
-#define CSR_MINIMAC_MDIO               MMPTR(0x80009004)
+#define CSR_MINIMAC_MDIO               MMPTR(0xe0009004)
 
 #define MINIMAC_MDIO_DO                        (0x1)
 #define MINIMAC_MDIO_DI                        (0x2)
 #define MINIMAC_MDIO_OE                        (0x4)
 #define MINIMAC_MDIO_CLK               (0x8)
 
-#define CSR_MINIMAC_STATE0             MMPTR(0x80009008)
-#define CSR_MINIMAC_ADDR0              MMPTR(0x8000900C)
-#define CSR_MINIMAC_COUNT0             MMPTR(0x80009010)
+#define CSR_MINIMAC_STATE0             MMPTR(0xe0009008)
+#define CSR_MINIMAC_ADDR0              MMPTR(0xe000900C)
+#define CSR_MINIMAC_COUNT0             MMPTR(0xe0009010)
 
-#define CSR_MINIMAC_STATE1             MMPTR(0x80009014)
-#define CSR_MINIMAC_ADDR1              MMPTR(0x80009018)
-#define CSR_MINIMAC_COUNT1             MMPTR(0x8000901C)
+#define CSR_MINIMAC_STATE1             MMPTR(0xe0009014)
+#define CSR_MINIMAC_ADDR1              MMPTR(0xe0009018)
+#define CSR_MINIMAC_COUNT1             MMPTR(0xe000901C)
 
-#define CSR_MINIMAC_STATE2             MMPTR(0x80009020)
-#define CSR_MINIMAC_ADDR2              MMPTR(0x80009024)
-#define CSR_MINIMAC_COUNT2             MMPTR(0x80009028)
+#define CSR_MINIMAC_STATE2             MMPTR(0xe0009020)
+#define CSR_MINIMAC_ADDR2              MMPTR(0xe0009024)
+#define CSR_MINIMAC_COUNT2             MMPTR(0xe0009028)
 
-#define CSR_MINIMAC_STATE3             MMPTR(0x8000902C)
-#define CSR_MINIMAC_ADDR3              MMPTR(0x80009030)
-#define CSR_MINIMAC_COUNT3             MMPTR(0x80009034)
+#define CSR_MINIMAC_STATE3             MMPTR(0xe000902C)
+#define CSR_MINIMAC_ADDR3              MMPTR(0xe0009030)
+#define CSR_MINIMAC_COUNT3             MMPTR(0xe0009034)
 
 #define MINIMAC_STATE_EMPTY            (0x0)
 #define MINIMAC_STATE_LOADED           (0x1)
 #define MINIMAC_STATE_PENDING          (0x2)
 
-#define CSR_MINIMAC_TXADR              MMPTR(0x80009038)
-#define CSR_MINIMAC_TXREMAINING                MMPTR(0x8000903C)
+#define CSR_MINIMAC_TXADR              MMPTR(0xe0009038)
+#define CSR_MINIMAC_TXREMAINING                MMPTR(0xe000903C)
 
 #endif /* __HW_MINIMAC_H */
index 954b9b9..6957819 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_PFPU_CTL           MMPTR(0x80005000)
+#define CSR_PFPU_CTL           MMPTR(0xe0005000)
 #define PFPU_CTL_START         0x01
 #define PFPU_CTL_BUSY          0x01
 
-#define CSR_PFPU_MESHBASE      MMPTR(0x80005004)
-#define CSR_PFPU_HMESHLAST     MMPTR(0x80005008)
-#define CSR_PFPU_VMESHLAST     MMPTR(0x8000500C)
+#define CSR_PFPU_MESHBASE      MMPTR(0xe0005004)
+#define CSR_PFPU_HMESHLAST     MMPTR(0xe0005008)
+#define CSR_PFPU_VMESHLAST     MMPTR(0xe000500C)
 
-#define CSR_PFPU_CODEPAGE      MMPTR(0x80005010)
+#define CSR_PFPU_CODEPAGE      MMPTR(0xe0005010)
 
-#define CSR_PFPU_VERTICES      MMPTR(0x80005014)
-#define CSR_PFPU_COLLISIONS    MMPTR(0x80005018)
-#define CSR_PFPU_STRAYWRITES   MMPTR(0x8000501C)
-#define CSR_PFPU_LASTDMA       MMPTR(0x80005020)
-#define CSR_PFPU_PC            MMPTR(0x80005024)
+#define CSR_PFPU_VERTICES      MMPTR(0xe0005014)
+#define CSR_PFPU_COLLISIONS    MMPTR(0xe0005018)
+#define CSR_PFPU_STRAYWRITES   MMPTR(0xe000501C)
+#define CSR_PFPU_LASTDMA       MMPTR(0xe0005020)
+#define CSR_PFPU_PC            MMPTR(0xe0005024)
 
-#define CSR_PFPU_DREGBASE      (0x80005400)
-#define CSR_PFPU_CODEBASE      (0x80005800)
+#define CSR_PFPU_DREGBASE      (0xe0005400)
+#define CSR_PFPU_CODEBASE      (0xe0005800)
 
 #define PFPU_OPCODE_NOP                (0x0)
 #define PFPU_OPCODE_FADD       (0x1)
index 2542f87..cbfb4ad 100644 (file)
@@ -20,6 +20,6 @@
 
 #include <hw/common.h>
 
-#define CSR_RC5_RX             MMPTR(0x8000c000)
+#define CSR_RC5_RX             MMPTR(0xe000c000)
 
 #endif /* __HW_RC5_H */
index 1dda8a8..d3ca09b 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_GPIO_IN            MMPTR(0x80001000)
-#define CSR_GPIO_OUT           MMPTR(0x80001004)
-#define CSR_GPIO_INTEN         MMPTR(0x80001008)
+#define CSR_GPIO_IN            MMPTR(0xe0001000)
+#define CSR_GPIO_OUT           MMPTR(0xe0001004)
+#define CSR_GPIO_INTEN         MMPTR(0xe0001008)
 
-#define CSR_TIMER0_CONTROL     MMPTR(0x80001010)
-#define CSR_TIMER0_COMPARE     MMPTR(0x80001014)
-#define CSR_TIMER0_COUNTER     MMPTR(0x80001018)
+#define CSR_TIMER0_CONTROL     MMPTR(0xe0001010)
+#define CSR_TIMER0_COMPARE     MMPTR(0xe0001014)
+#define CSR_TIMER0_COUNTER     MMPTR(0xe0001018)
 
-#define CSR_TIMER1_CONTROL     MMPTR(0x80001020)
-#define CSR_TIMER1_COMPARE     MMPTR(0x80001024)
-#define CSR_TIMER1_COUNTER     MMPTR(0x80001028)
+#define CSR_TIMER1_CONTROL     MMPTR(0xe0001020)
+#define CSR_TIMER1_COMPARE     MMPTR(0xe0001024)
+#define CSR_TIMER1_COUNTER     MMPTR(0xe0001028)
 
 #define TIMER_ENABLE           (0x01)
 #define TIMER_AUTORESTART      (0x02)
 
-#define CSR_CAPABILITIES       MMPTR(0x80001038)
-#define CSR_SYSTEM_ID          MMPTR(0x8000103c)
+#define CSR_CAPABILITIES       MMPTR(0xe0001038)
+#define CSR_SYSTEM_ID          MMPTR(0xe000103c)
 
 #endif /* __HW_SYSCTL_H */
diff --git a/software/include/hw/tags b/software/include/hw/tags
new file mode 100644 (file)
index 0000000..36f91f9
--- /dev/null
@@ -0,0 +1,246 @@
+!_TAG_FILE_FORMAT      2       /extended format; --format=1 will not append ;" to lines/
+!_TAG_FILE_SORTED      1       /0=unsorted, 1=sorted, 2=foldcase/
+!_TAG_PROGRAM_AUTHOR   Darren Hiebert  /dhiebert@users.sourceforge.net/
+!_TAG_PROGRAM_NAME     Exuberant Ctags //
+!_TAG_PROGRAM_URL      http://ctags.sourceforge.net    /official site/
+!_TAG_PROGRAM_VERSION  5.8     //
+AC97_CRCTL_RQEN        /home/mw/repo/milkymist/software/include/hw/ac97.h      25;"    d
+AC97_CRCTL_WRITE       /home/mw/repo/milkymist/software/include/hw/ac97.h      26;"    d
+AC97_MAX_DMASIZE       /home/mw/repo/milkymist/software/include/hw/ac97.h      42;"    d
+AC97_SCTL_EN   /home/mw/repo/milkymist/software/include/hw/ac97.h      40;"    d
+BT656CAP_FILTERSTATUS_FIELD1   /home/mw/repo/milkymist/software/include/hw/bt656cap.h  34;"    d
+BT656CAP_FILTERSTATUS_FIELD2   /home/mw/repo/milkymist/software/include/hw/bt656cap.h  35;"    d
+BT656CAP_FILTERSTATUS_INFRAME  /home/mw/repo/milkymist/software/include/hw/bt656cap.h  36;"    d
+BT656CAP_I2C_SDAIN     /home/mw/repo/milkymist/software/include/hw/bt656cap.h  29;"    d
+BT656CAP_I2C_SDAOE     /home/mw/repo/milkymist/software/include/hw/bt656cap.h  31;"    d
+BT656CAP_I2C_SDAOUT    /home/mw/repo/milkymist/software/include/hw/bt656cap.h  30;"    d
+BT656CAP_I2C_SDC       /home/mw/repo/milkymist/software/include/hw/bt656cap.h  32;"    d
+CSR_AC97_CRADDR        /home/mw/repo/milkymist/software/include/hw/ac97.h      28;"    d
+CSR_AC97_CRCTL /home/mw/repo/milkymist/software/include/hw/ac97.h      23;"    d
+CSR_AC97_CRDATAIN      /home/mw/repo/milkymist/software/include/hw/ac97.h      30;"    d
+CSR_AC97_CRDATAOUT     /home/mw/repo/milkymist/software/include/hw/ac97.h      29;"    d
+CSR_AC97_DADDRESS      /home/mw/repo/milkymist/software/include/hw/ac97.h      33;"    d
+CSR_AC97_DCTL  /home/mw/repo/milkymist/software/include/hw/ac97.h      32;"    d
+CSR_AC97_DREMAINING    /home/mw/repo/milkymist/software/include/hw/ac97.h      34;"    d
+CSR_AC97_UADDRESS      /home/mw/repo/milkymist/software/include/hw/ac97.h      37;"    d
+CSR_AC97_UCTL  /home/mw/repo/milkymist/software/include/hw/ac97.h      36;"    d
+CSR_AC97_UREMAINING    /home/mw/repo/milkymist/software/include/hw/ac97.h      38;"    d
+CSR_BT656CAP_BASE      /home/mw/repo/milkymist/software/include/hw/bt656cap.h  25;"    d
+CSR_BT656CAP_DONEBURSTS        /home/mw/repo/milkymist/software/include/hw/bt656cap.h  27;"    d
+CSR_BT656CAP_FILTERSTATUS      /home/mw/repo/milkymist/software/include/hw/bt656cap.h  24;"    d
+CSR_BT656CAP_I2C       /home/mw/repo/milkymist/software/include/hw/bt656cap.h  23;"    d
+CSR_BT656CAP_MAXBURSTS /home/mw/repo/milkymist/software/include/hw/bt656cap.h  26;"    d
+CSR_CAPABILITIES       /home/mw/repo/milkymist/software/include/hw/sysctl.h    38;"    d
+CSR_FMLMETER_ACKCOUNT  /home/mw/repo/milkymist/software/include/hw/fmlmeter.h  28;"    d
+CSR_FMLMETER_ENABLE    /home/mw/repo/milkymist/software/include/hw/fmlmeter.h  23;"    d
+CSR_FMLMETER_STBCOUNT  /home/mw/repo/milkymist/software/include/hw/fmlmeter.h  27;"    d
+CSR_GPIO_IN    /home/mw/repo/milkymist/software/include/hw/sysctl.h    23;"    d
+CSR_GPIO_INTEN /home/mw/repo/milkymist/software/include/hw/sysctl.h    25;"    d
+CSR_GPIO_OUT   /home/mw/repo/milkymist/software/include/hw/sysctl.h    24;"    d
+CSR_HPDMC_BYPASS       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     29;"    d
+CSR_HPDMC_IODELAY      /home/mw/repo/milkymist/software/include/hw/hpdmc.h     47;"    d
+CSR_HPDMC_SYSTEM       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     23;"    d
+CSR_HPDMC_TIMING       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     38;"    d
+CSR_MIDI_DIVISOR       /home/mw/repo/milkymist/software/include/hw/midi.h      24;"    d
+CSR_MIDI_RXTX  /home/mw/repo/milkymist/software/include/hw/midi.h      23;"    d
+CSR_MINIMAC_ADDR0      /home/mw/repo/milkymist/software/include/hw/minimac.h   36;"    d
+CSR_MINIMAC_ADDR1      /home/mw/repo/milkymist/software/include/hw/minimac.h   40;"    d
+CSR_MINIMAC_ADDR2      /home/mw/repo/milkymist/software/include/hw/minimac.h   44;"    d
+CSR_MINIMAC_ADDR3      /home/mw/repo/milkymist/software/include/hw/minimac.h   48;"    d
+CSR_MINIMAC_COUNT0     /home/mw/repo/milkymist/software/include/hw/minimac.h   37;"    d
+CSR_MINIMAC_COUNT1     /home/mw/repo/milkymist/software/include/hw/minimac.h   41;"    d
+CSR_MINIMAC_COUNT2     /home/mw/repo/milkymist/software/include/hw/minimac.h   45;"    d
+CSR_MINIMAC_COUNT3     /home/mw/repo/milkymist/software/include/hw/minimac.h   49;"    d
+CSR_MINIMAC_MDIO       /home/mw/repo/milkymist/software/include/hw/minimac.h   28;"    d
+CSR_MINIMAC_SETUP      /home/mw/repo/milkymist/software/include/hw/minimac.h   23;"    d
+CSR_MINIMAC_STATE0     /home/mw/repo/milkymist/software/include/hw/minimac.h   35;"    d
+CSR_MINIMAC_STATE1     /home/mw/repo/milkymist/software/include/hw/minimac.h   39;"    d
+CSR_MINIMAC_STATE2     /home/mw/repo/milkymist/software/include/hw/minimac.h   43;"    d
+CSR_MINIMAC_STATE3     /home/mw/repo/milkymist/software/include/hw/minimac.h   47;"    d
+CSR_MINIMAC_TXADR      /home/mw/repo/milkymist/software/include/hw/minimac.h   55;"    d
+CSR_MINIMAC_TXREMAINING        /home/mw/repo/milkymist/software/include/hw/minimac.h   56;"    d
+CSR_PFPU_CODEBASE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      40;"    d
+CSR_PFPU_CODEPAGE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      31;"    d
+CSR_PFPU_COLLISIONS    /home/mw/repo/milkymist/software/include/hw/pfpu.h      34;"    d
+CSR_PFPU_CTL   /home/mw/repo/milkymist/software/include/hw/pfpu.h      23;"    d
+CSR_PFPU_DREGBASE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      39;"    d
+CSR_PFPU_HMESHLAST     /home/mw/repo/milkymist/software/include/hw/pfpu.h      28;"    d
+CSR_PFPU_LASTDMA       /home/mw/repo/milkymist/software/include/hw/pfpu.h      36;"    d
+CSR_PFPU_MESHBASE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      27;"    d
+CSR_PFPU_PC    /home/mw/repo/milkymist/software/include/hw/pfpu.h      37;"    d
+CSR_PFPU_STRAYWRITES   /home/mw/repo/milkymist/software/include/hw/pfpu.h      35;"    d
+CSR_PFPU_VERTICES      /home/mw/repo/milkymist/software/include/hw/pfpu.h      33;"    d
+CSR_PFPU_VMESHLAST     /home/mw/repo/milkymist/software/include/hw/pfpu.h      29;"    d
+CSR_RC5_RX     /home/mw/repo/milkymist/software/include/hw/rc5.h       23;"    d
+CSR_SYSTEM_ID  /home/mw/repo/milkymist/software/include/hw/sysctl.h    39;"    d
+CSR_TIMER0_COMPARE     /home/mw/repo/milkymist/software/include/hw/sysctl.h    28;"    d
+CSR_TIMER0_CONTROL     /home/mw/repo/milkymist/software/include/hw/sysctl.h    27;"    d
+CSR_TIMER0_COUNTER     /home/mw/repo/milkymist/software/include/hw/sysctl.h    29;"    d
+CSR_TIMER1_COMPARE     /home/mw/repo/milkymist/software/include/hw/sysctl.h    32;"    d
+CSR_TIMER1_CONTROL     /home/mw/repo/milkymist/software/include/hw/sysctl.h    31;"    d
+CSR_TIMER1_COUNTER     /home/mw/repo/milkymist/software/include/hw/sysctl.h    33;"    d
+CSR_TMU_ALPHA  /home/mw/repo/milkymist/software/include/hw/tmu.h       54;"    d
+CSR_TMU_BRIGHTNESS     /home/mw/repo/milkymist/software/include/hw/tmu.h       30;"    d
+CSR_TMU_CHROMAKEY      /home/mw/repo/milkymist/software/include/hw/tmu.h       31;"    d
+CSR_TMU_CTL    /home/mw/repo/milkymist/software/include/hw/tmu.h       23;"    d
+CSR_TMU_DSTFBUF        /home/mw/repo/milkymist/software/include/hw/tmu.h       46;"    d
+CSR_TMU_DSTHOFFSET     /home/mw/repo/milkymist/software/include/hw/tmu.h       49;"    d
+CSR_TMU_DSTHRES        /home/mw/repo/milkymist/software/include/hw/tmu.h       47;"    d
+CSR_TMU_DSTSQUAREH     /home/mw/repo/milkymist/software/include/hw/tmu.h       52;"    d
+CSR_TMU_DSTSQUAREW     /home/mw/repo/milkymist/software/include/hw/tmu.h       51;"    d
+CSR_TMU_DSTVOFFSET     /home/mw/repo/milkymist/software/include/hw/tmu.h       50;"    d
+CSR_TMU_DSTVRES        /home/mw/repo/milkymist/software/include/hw/tmu.h       48;"    d
+CSR_TMU_HIT_A  /home/mw/repo/milkymist/software/include/hw/tmu.h       68;"    d
+CSR_TMU_HIT_B  /home/mw/repo/milkymist/software/include/hw/tmu.h       70;"    d
+CSR_TMU_HIT_C  /home/mw/repo/milkymist/software/include/hw/tmu.h       72;"    d
+CSR_TMU_HIT_D  /home/mw/repo/milkymist/software/include/hw/tmu.h       74;"    d
+CSR_TMU_HMESHLAST      /home/mw/repo/milkymist/software/include/hw/tmu.h       28;"    d
+CSR_TMU_REQ_A  /home/mw/repo/milkymist/software/include/hw/tmu.h       67;"    d
+CSR_TMU_REQ_B  /home/mw/repo/milkymist/software/include/hw/tmu.h       69;"    d
+CSR_TMU_REQ_C  /home/mw/repo/milkymist/software/include/hw/tmu.h       71;"    d
+CSR_TMU_REQ_D  /home/mw/repo/milkymist/software/include/hw/tmu.h       73;"    d
+CSR_TMU_TEXFBUF        /home/mw/repo/milkymist/software/include/hw/tmu.h       36;"    d
+CSR_TMU_TEXHMASK       /home/mw/repo/milkymist/software/include/hw/tmu.h       39;"    d
+CSR_TMU_TEXHRES        /home/mw/repo/milkymist/software/include/hw/tmu.h       37;"    d
+CSR_TMU_TEXVMASK       /home/mw/repo/milkymist/software/include/hw/tmu.h       40;"    d
+CSR_TMU_TEXVRES        /home/mw/repo/milkymist/software/include/hw/tmu.h       38;"    d
+CSR_TMU_VERTICESADR    /home/mw/repo/milkymist/software/include/hw/tmu.h       35;"    d
+CSR_TMU_VMESHLAST      /home/mw/repo/milkymist/software/include/hw/tmu.h       29;"    d
+CSR_UART_DIVISOR       /home/mw/repo/milkymist/software/include/hw/uart.h      24;"    d
+CSR_UART_RXTX  /home/mw/repo/milkymist/software/include/hw/uart.h      23;"    d
+CSR_VGA_BASEADDRESS    /home/mw/repo/milkymist/software/include/hw/vga.h       37;"    d
+CSR_VGA_BASEADDRESS_ACT        /home/mw/repo/milkymist/software/include/hw/vga.h       38;"    d
+CSR_VGA_BURST_COUNT    /home/mw/repo/milkymist/software/include/hw/vga.h       40;"    d
+CSR_VGA_DDC    /home/mw/repo/milkymist/software/include/hw/vga.h       42;"    d
+CSR_VGA_HRES   /home/mw/repo/milkymist/software/include/hw/vga.h       27;"    d
+CSR_VGA_HSCAN  /home/mw/repo/milkymist/software/include/hw/vga.h       30;"    d
+CSR_VGA_HSYNC_END      /home/mw/repo/milkymist/software/include/hw/vga.h       29;"    d
+CSR_VGA_HSYNC_START    /home/mw/repo/milkymist/software/include/hw/vga.h       28;"    d
+CSR_VGA_RESET  /home/mw/repo/milkymist/software/include/hw/vga.h       23;"    d
+CSR_VGA_VRES   /home/mw/repo/milkymist/software/include/hw/vga.h       32;"    d
+CSR_VGA_VSCAN  /home/mw/repo/milkymist/software/include/hw/vga.h       35;"    d
+CSR_VGA_VSYNC_END      /home/mw/repo/milkymist/software/include/hw/vga.h       34;"    d
+CSR_VGA_VSYNC_START    /home/mw/repo/milkymist/software/include/hw/vga.h       33;"    d
+FMLMETER_ENABLE        /home/mw/repo/milkymist/software/include/hw/fmlmeter.h  25;"    d
+HPDMC_BYPASS_A_S       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     35;"    d
+HPDMC_BYPASS_BA_S      /home/mw/repo/milkymist/software/include/hw/hpdmc.h     36;"    d
+HPDMC_BYPASS_CAS       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     33;"    d
+HPDMC_BYPASS_CS        /home/mw/repo/milkymist/software/include/hw/hpdmc.h     31;"    d
+HPDMC_BYPASS_RAS       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     34;"    d
+HPDMC_BYPASS_WE        /home/mw/repo/milkymist/software/include/hw/hpdmc.h     32;"    d
+HPDMC_DQSDELAY_CE      /home/mw/repo/milkymist/software/include/hw/hpdmc.h     53;"    d
+HPDMC_DQSDELAY_INC     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     54;"    d
+HPDMC_DQSDELAY_RDY     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     55;"    d
+HPDMC_IDELAY_CE        /home/mw/repo/milkymist/software/include/hw/hpdmc.h     50;"    d
+HPDMC_IDELAY_INC       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     51;"    d
+HPDMC_IDELAY_RST       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     49;"    d
+HPDMC_PLL1_LOCKED      /home/mw/repo/milkymist/software/include/hw/hpdmc.h     57;"    d
+HPDMC_PLL2_LOCKED      /home/mw/repo/milkymist/software/include/hw/hpdmc.h     58;"    d
+HPDMC_SYSTEM_BYPASS    /home/mw/repo/milkymist/software/include/hw/hpdmc.h     25;"    d
+HPDMC_SYSTEM_CKE       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     27;"    d
+HPDMC_SYSTEM_RESET     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     26;"    d
+HPDMC_TIMING_CL3       /home/mw/repo/milkymist/software/include/hw/hpdmc.h     42;"    d
+HPDMC_TIMING_TRCD_S    /home/mw/repo/milkymist/software/include/hw/hpdmc.h     41;"    d
+HPDMC_TIMING_TREFI_S   /home/mw/repo/milkymist/software/include/hw/hpdmc.h     43;"    d
+HPDMC_TIMING_TRFC_S    /home/mw/repo/milkymist/software/include/hw/hpdmc.h     44;"    d
+HPDMC_TIMING_TRP_S     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     40;"    d
+HPDMC_TIMING_TWR_S     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     45;"    d
+MINIMAC_MDIO_CLK       /home/mw/repo/milkymist/software/include/hw/minimac.h   33;"    d
+MINIMAC_MDIO_DI        /home/mw/repo/milkymist/software/include/hw/minimac.h   31;"    d
+MINIMAC_MDIO_DO        /home/mw/repo/milkymist/software/include/hw/minimac.h   30;"    d
+MINIMAC_MDIO_OE        /home/mw/repo/milkymist/software/include/hw/minimac.h   32;"    d
+MINIMAC_SETUP_RXRST    /home/mw/repo/milkymist/software/include/hw/minimac.h   25;"    d
+MINIMAC_SETUP_TXRST    /home/mw/repo/milkymist/software/include/hw/minimac.h   26;"    d
+MINIMAC_STATE_EMPTY    /home/mw/repo/milkymist/software/include/hw/minimac.h   51;"    d
+MINIMAC_STATE_LOADED   /home/mw/repo/milkymist/software/include/hw/minimac.h   52;"    d
+MINIMAC_STATE_PENDING  /home/mw/repo/milkymist/software/include/hw/minimac.h   53;"    d
+PFPU_CTL_BUSY  /home/mw/repo/milkymist/software/include/hw/pfpu.h      25;"    d
+PFPU_CTL_START /home/mw/repo/milkymist/software/include/hw/pfpu.h      24;"    d
+PFPU_LATENCY_ABOVE     /home/mw/repo/milkymist/software/include/hw/pfpu.h      68;"    d
+PFPU_LATENCY_COPY      /home/mw/repo/milkymist/software/include/hw/pfpu.h      70;"    d
+PFPU_LATENCY_COS       /home/mw/repo/milkymist/software/include/hw/pfpu.h      67;"    d
+PFPU_LATENCY_EQUAL     /home/mw/repo/milkymist/software/include/hw/pfpu.h      69;"    d
+PFPU_LATENCY_F2I       /home/mw/repo/milkymist/software/include/hw/pfpu.h      63;"    d
+PFPU_LATENCY_FABS      /home/mw/repo/milkymist/software/include/hw/pfpu.h      62;"    d
+PFPU_LATENCY_FADD      /home/mw/repo/milkymist/software/include/hw/pfpu.h      59;"    d
+PFPU_LATENCY_FMUL      /home/mw/repo/milkymist/software/include/hw/pfpu.h      61;"    d
+PFPU_LATENCY_FSUB      /home/mw/repo/milkymist/software/include/hw/pfpu.h      60;"    d
+PFPU_LATENCY_I2F       /home/mw/repo/milkymist/software/include/hw/pfpu.h      64;"    d
+PFPU_LATENCY_IF        /home/mw/repo/milkymist/software/include/hw/pfpu.h      71;"    d
+PFPU_LATENCY_QUAKE     /home/mw/repo/milkymist/software/include/hw/pfpu.h      73;"    d
+PFPU_LATENCY_SIN       /home/mw/repo/milkymist/software/include/hw/pfpu.h      66;"    d
+PFPU_LATENCY_TSIGN     /home/mw/repo/milkymist/software/include/hw/pfpu.h      72;"    d
+PFPU_LATENCY_VECTOUT   /home/mw/repo/milkymist/software/include/hw/pfpu.h      65;"    d
+PFPU_OPCODE_ABOVE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      52;"    d
+PFPU_OPCODE_COPY       /home/mw/repo/milkymist/software/include/hw/pfpu.h      54;"    d
+PFPU_OPCODE_COS        /home/mw/repo/milkymist/software/include/hw/pfpu.h      51;"    d
+PFPU_OPCODE_EQUAL      /home/mw/repo/milkymist/software/include/hw/pfpu.h      53;"    d
+PFPU_OPCODE_F2I        /home/mw/repo/milkymist/software/include/hw/pfpu.h      47;"    d
+PFPU_OPCODE_FABS       /home/mw/repo/milkymist/software/include/hw/pfpu.h      46;"    d
+PFPU_OPCODE_FADD       /home/mw/repo/milkymist/software/include/hw/pfpu.h      43;"    d
+PFPU_OPCODE_FMUL       /home/mw/repo/milkymist/software/include/hw/pfpu.h      45;"    d
+PFPU_OPCODE_FSUB       /home/mw/repo/milkymist/software/include/hw/pfpu.h      44;"    d
+PFPU_OPCODE_I2F        /home/mw/repo/milkymist/software/include/hw/pfpu.h      48;"    d
+PFPU_OPCODE_IF /home/mw/repo/milkymist/software/include/hw/pfpu.h      55;"    d
+PFPU_OPCODE_NOP        /home/mw/repo/milkymist/software/include/hw/pfpu.h      42;"    d
+PFPU_OPCODE_QUAKE      /home/mw/repo/milkymist/software/include/hw/pfpu.h      57;"    d
+PFPU_OPCODE_SIN        /home/mw/repo/milkymist/software/include/hw/pfpu.h      50;"    d
+PFPU_OPCODE_TSIGN      /home/mw/repo/milkymist/software/include/hw/pfpu.h      56;"    d
+PFPU_OPCODE_VECTOUT    /home/mw/repo/milkymist/software/include/hw/pfpu.h      49;"    d
+PFPU_PAGESIZE  /home/mw/repo/milkymist/software/include/hw/pfpu.h      76;"    d
+PFPU_PROGSIZE  /home/mw/repo/milkymist/software/include/hw/pfpu.h      75;"    d
+PFPU_REG_COUNT /home/mw/repo/milkymist/software/include/hw/pfpu.h      78;"    d
+PFPU_REG_IFB   /home/mw/repo/milkymist/software/include/hw/pfpu.h      83;"    d
+PFPU_REG_X     /home/mw/repo/milkymist/software/include/hw/pfpu.h      80;"    d
+PFPU_REG_Y     /home/mw/repo/milkymist/software/include/hw/pfpu.h      81;"    d
+PFPU_SPREG_COUNT       /home/mw/repo/milkymist/software/include/hw/pfpu.h      79;"    d
+PFPU_TRIG_CONV /home/mw/repo/milkymist/software/include/hw/pfpu.h      85;"    d
+SDRAM_BASE     /home/mw/repo/milkymist/software/include/hw/hpdmc.h     60;"    d
+TIMER_AUTORESTART      /home/mw/repo/milkymist/software/include/hw/sysctl.h    36;"    d
+TIMER_ENABLE   /home/mw/repo/milkymist/software/include/hw/sysctl.h    35;"    d
+TMU_ALPHA_MAX  /home/mw/repo/milkymist/software/include/hw/tmu.h       56;"    d
+TMU_BRIGHTNESS_MAX     /home/mw/repo/milkymist/software/include/hw/tmu.h       33;"    d
+TMU_CTL_BUSY   /home/mw/repo/milkymist/software/include/hw/tmu.h       25;"    d
+TMU_CTL_CHROMAKEY      /home/mw/repo/milkymist/software/include/hw/tmu.h       26;"    d
+TMU_CTL_START  /home/mw/repo/milkymist/software/include/hw/tmu.h       24;"    d
+TMU_FIXEDPOINT_SHIFT   /home/mw/repo/milkymist/software/include/hw/tmu.h       44;"    d
+TMU_MASK_FULL  /home/mw/repo/milkymist/software/include/hw/tmu.h       43;"    d
+TMU_MASK_NOFILTER      /home/mw/repo/milkymist/software/include/hw/tmu.h       42;"    d
+TMU_MESH_MAXSIZE       /home/mw/repo/milkymist/software/include/hw/tmu.h       63;"    d
+VGA_DDC_SDAIN  /home/mw/repo/milkymist/software/include/hw/vga.h       44;"    d
+VGA_DDC_SDAOE  /home/mw/repo/milkymist/software/include/hw/vga.h       46;"    d
+VGA_DDC_SDAOUT /home/mw/repo/milkymist/software/include/hw/vga.h       45;"    d
+VGA_DDC_SDC    /home/mw/repo/milkymist/software/include/hw/vga.h       47;"    d
+VGA_RESET      /home/mw/repo/milkymist/software/include/hw/vga.h       25;"    d
+__HW_AC97_H    /home/mw/repo/milkymist/software/include/hw/ac97.h      19;"    d
+__HW_BT656CAP_H        /home/mw/repo/milkymist/software/include/hw/bt656cap.h  19;"    d
+__HW_FMLMETER_H        /home/mw/repo/milkymist/software/include/hw/fmlmeter.h  19;"    d
+__HW_HPDMC_H   /home/mw/repo/milkymist/software/include/hw/hpdmc.h     19;"    d
+__HW_MIDI_H    /home/mw/repo/milkymist/software/include/hw/midi.h      19;"    d
+__HW_MINIMAC_H /home/mw/repo/milkymist/software/include/hw/minimac.h   19;"    d
+__HW_PFPU_H    /home/mw/repo/milkymist/software/include/hw/pfpu.h      19;"    d
+__HW_RC5_H     /home/mw/repo/milkymist/software/include/hw/rc5.h       19;"    d
+__HW_SYSCTL_H  /home/mw/repo/milkymist/software/include/hw/sysctl.h    19;"    d
+__HW_TMU_H     /home/mw/repo/milkymist/software/include/hw/tmu.h       19;"    d
+__HW_UART_H    /home/mw/repo/milkymist/software/include/hw/uart.h      19;"    d
+__HW_VGA_H     /home/mw/repo/milkymist/software/include/hw/vga.h       19;"    d
+__anon1::__anon2::dest /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned dest:7;$/;"    m       struct:__anon1::__anon2 access:public
+__anon1::__anon2::opa  /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opa:7;$/;"     m       struct:__anon1::__anon2 access:public
+__anon1::__anon2::opb  /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opb:7;$/;"     m       struct:__anon1::__anon2 access:public
+__anon1::__anon2::opcode       /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opcode:4;$/;"  m       struct:__anon1::__anon2 access:public
+__anon1::__anon2::pad  /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned pad:7;$/;"     m       struct:__anon1::__anon2 access:public
+__anon1::i     /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^      } i __attribute__((packed));$/;"        m       union:__anon1   typeref:struct:__anon1::__anon2 access:public
+__anon1::w     /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^      unsigned int w;$/;"     m       union:__anon1   access:public
+dest   /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned dest:7;$/;"    m       struct:__anon1::__anon2 access:public
+i      /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^      } i __attribute__((packed));$/;"        m       union:__anon1   typeref:struct:__anon1::__anon2 access:public
+opa    /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opa:7;$/;"     m       struct:__anon1::__anon2 access:public
+opb    /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opb:7;$/;"     m       struct:__anon1::__anon2 access:public
+opcode /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned opcode:4;$/;"  m       struct:__anon1::__anon2 access:public
+pad    /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^              unsigned pad:7;$/;"     m       struct:__anon1::__anon2 access:public
+pfpu_instruction       /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^} pfpu_instruction;$/;"       t       typeref:union:__anon1
+tmu_vertex     /home/mw/repo/milkymist/software/include/hw/tmu.h       /^struct tmu_vertex {$/;"       s
+tmu_vertex::x  /home/mw/repo/milkymist/software/include/hw/tmu.h       /^      int x;$/;"      m       struct:tmu_vertex       access:public
+tmu_vertex::y  /home/mw/repo/milkymist/software/include/hw/tmu.h       /^      int y;$/;"      m       struct:tmu_vertex       access:public
+w      /home/mw/repo/milkymist/software/include/hw/pfpu.h      /^      unsigned int w;$/;"     m       union:__anon1   access:public
+x      /home/mw/repo/milkymist/software/include/hw/tmu.h       /^      int x;$/;"      m       struct:tmu_vertex       access:public
+y      /home/mw/repo/milkymist/software/include/hw/tmu.h       /^      int y;$/;"      m       struct:tmu_vertex       access:public
index fa12f3c..1b578ae 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_TMU_CTL            MMPTR(0x80006000)
+#define CSR_TMU_CTL            MMPTR(0xe0006000)
 #define TMU_CTL_START          0x01
 #define TMU_CTL_BUSY           0x01
 #define TMU_CTL_CHROMAKEY      0x02
 
-#define CSR_TMU_HMESHLAST      MMPTR(0x80006004)
-#define CSR_TMU_VMESHLAST      MMPTR(0x80006008)
-#define CSR_TMU_BRIGHTNESS     MMPTR(0x8000600C)
-#define CSR_TMU_CHROMAKEY      MMPTR(0x80006010)
+#define CSR_TMU_HMESHLAST      MMPTR(0xe0006004)
+#define CSR_TMU_VMESHLAST      MMPTR(0xe0006008)
+#define CSR_TMU_BRIGHTNESS     MMPTR(0xe000600C)
+#define CSR_TMU_CHROMAKEY      MMPTR(0xe0006010)
 
 #define TMU_BRIGHTNESS_MAX     (63)
 
-#define CSR_TMU_VERTICESADR    MMPTR(0x80006014)
-#define CSR_TMU_TEXFBUF                MMPTR(0x80006018)
-#define CSR_TMU_TEXHRES                MMPTR(0x8000601C)
-#define CSR_TMU_TEXVRES                MMPTR(0x80006020)
-#define CSR_TMU_TEXHMASK       MMPTR(0x80006024)
-#define CSR_TMU_TEXVMASK       MMPTR(0x80006028)
+#define CSR_TMU_VERTICESADR    MMPTR(0xe0006014)
+#define CSR_TMU_TEXFBUF                MMPTR(0xe0006018)
+#define CSR_TMU_TEXHRES                MMPTR(0xe000601C)
+#define CSR_TMU_TEXVRES                MMPTR(0xe0006020)
+#define CSR_TMU_TEXHMASK       MMPTR(0xe0006024)
+#define CSR_TMU_TEXVMASK       MMPTR(0xe0006028)
 
 #define TMU_MASK_NOFILTER      (0x3ffc0)
 #define TMU_MASK_FULL          (0x3ffff)
 #define TMU_FIXEDPOINT_SHIFT   (6)
 
-#define CSR_TMU_DSTFBUF                MMPTR(0x8000602C)
-#define CSR_TMU_DSTHRES                MMPTR(0x80006030)
-#define CSR_TMU_DSTVRES                MMPTR(0x80006034)
-#define CSR_TMU_DSTHOFFSET     MMPTR(0x80006038)
-#define CSR_TMU_DSTVOFFSET     MMPTR(0x8000603C)
-#define CSR_TMU_DSTSQUAREW     MMPTR(0x80006040)
-#define CSR_TMU_DSTSQUAREH     MMPTR(0x80006044)
+#define CSR_TMU_DSTFBUF                MMPTR(0xe000602C)
+#define CSR_TMU_DSTHRES                MMPTR(0xe0006030)
+#define CSR_TMU_DSTVRES                MMPTR(0xe0006034)
+#define CSR_TMU_DSTHOFFSET     MMPTR(0xe0006038)
+#define CSR_TMU_DSTVOFFSET     MMPTR(0xe000603C)
+#define CSR_TMU_DSTSQUAREW     MMPTR(0xe0006040)
+#define CSR_TMU_DSTSQUAREH     MMPTR(0xe0006044)
 
-#define CSR_TMU_ALPHA          MMPTR(0x80006048)
+#define CSR_TMU_ALPHA          MMPTR(0xe0006048)
 
 #define TMU_ALPHA_MAX          (63)
 
@@ -64,14 +64,14 @@ struct tmu_vertex {
 
 /* Performance monitoring */
 
-#define CSR_TMU_REQ_A          MMPTR(0x80006050)
-#define CSR_TMU_HIT_A          MMPTR(0x80006054)
-#define CSR_TMU_REQ_B          MMPTR(0x80006058)
-#define CSR_TMU_HIT_B          MMPTR(0x8000605C)
-#define CSR_TMU_REQ_C          MMPTR(0x80006060)
-#define CSR_TMU_HIT_C          MMPTR(0x80006064)
-#define CSR_TMU_REQ_D          MMPTR(0x80006068)
-#define CSR_TMU_HIT_D          MMPTR(0x8000606C)
+#define CSR_TMU_REQ_A          MMPTR(0xe0006050)
+#define CSR_TMU_HIT_A          MMPTR(0xe0006054)
+#define CSR_TMU_REQ_B          MMPTR(0xe0006058)
+#define CSR_TMU_HIT_B          MMPTR(0xe000605C)
+#define CSR_TMU_REQ_C          MMPTR(0xe0006060)
+#define CSR_TMU_HIT_C          MMPTR(0xe0006064)
+#define CSR_TMU_REQ_D          MMPTR(0xe0006068)
+#define CSR_TMU_HIT_D          MMPTR(0xe000606C)
 
 #endif /* __HW_TMU_H */
 
index e4cef8e..0cbe999 100644 (file)
@@ -20,7 +20,7 @@
 
 #include <hw/common.h>
 
-#define CSR_UART_RXTX          MMPTR(0x80000000)
-#define CSR_UART_DIVISOR       MMPTR(0x80000004)
+#define CSR_UART_RXTX          MMPTR(0xe0000000)
+#define CSR_UART_DIVISOR       MMPTR(0xe0000004)
 
 #endif /* __HW_UART_H */
index ada7907..ba1bd1a 100644 (file)
 
 #include <hw/common.h>
 
-#define CSR_VGA_RESET          MMPTR(0x80003000)
+#define CSR_VGA_RESET          MMPTR(0xe0003000)
 
 #define VGA_RESET              (0x01)
 
-#define CSR_VGA_HRES           MMPTR(0x80003004)
-#define CSR_VGA_HSYNC_START    MMPTR(0x80003008)
-#define CSR_VGA_HSYNC_END      MMPTR(0x8000300C)
-#define CSR_VGA_HSCAN          MMPTR(0x80003010)
+#define CSR_VGA_HRES           MMPTR(0xe0003004)
+#define CSR_VGA_HSYNC_START    MMPTR(0xe0003008)
+#define CSR_VGA_HSYNC_END      MMPTR(0xe000300C)
+#define CSR_VGA_HSCAN          MMPTR(0xe0003010)
 
-#define CSR_VGA_VRES           MMPTR(0x80003014)
-#define CSR_VGA_VSYNC_START    MMPTR(0x80003018)
-#define CSR_VGA_VSYNC_END      MMPTR(0x8000301C)
-#define CSR_VGA_VSCAN          MMPTR(0x80003020)
+#define CSR_VGA_VRES           MMPTR(0xe0003014)
+#define CSR_VGA_VSYNC_START    MMPTR(0xe0003018)
+#define CSR_VGA_VSYNC_END      MMPTR(0xe000301C)
+#define CSR_VGA_VSCAN          MMPTR(0xe0003020)
 
-#define CSR_VGA_BASEADDRESS    MMPTR(0x80003024)
-#define CSR_VGA_BASEADDRESS_ACT        MMPTR(0x80003028)
+#define CSR_VGA_BASEADDRESS    MMPTR(0xe0003024)
+#define CSR_VGA_BASEADDRESS_ACT        MMPTR(0xe0003028)
 
-#define CSR_VGA_BURST_COUNT    MMPTR(0x8000302C)
+#define CSR_VGA_BURST_COUNT    MMPTR(0xe000302C)
 
-#define CSR_VGA_DDC            MMPTR(0x80003030)
+#define CSR_VGA_DDC            MMPTR(0xe0003030)
 
 #define VGA_DDC_SDAIN          (0x1)
 #define VGA_DDC_SDAOUT         (0x2)