Remove BRAM core
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Mon, 17 May 2010 18:18:30 +0000 (20:18 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Mon, 17 May 2010 18:18:30 +0000 (20:18 +0200)
boards/milkymist-one/rtl/system.v
boards/milkymist-one/sources.mak
boards/xilinx-ml401/rtl/system.v
boards/xilinx-ml401/sources.mak
clean_all.sh
cores/bram/doc/Makefile [deleted file]
cores/bram/doc/bram.tex [deleted file]
cores/bram/rtl/bram.v [deleted file]
cores/tmu2/rtl/tmu2_texcache.v
doc/system.tex

index 8f49f24..540df04 100644 (file)
@@ -247,48 +247,32 @@ wire              cpuibus_ack,
 //------------------------------------------------------------------
 wire [31:0]    brg_adr,
                norflash_adr,
-               bram_adr,
-               csrbrg_adr,
-               isp1362_adr;
+               csrbrg_adr;
 
-wire [2:0]     brg_cti,
-               bram_cti;
+wire [2:0]     brg_cti;
 
 wire [31:0]    brg_dat_r,
                brg_dat_w,
                norflash_dat_r,
-               bram_dat_r,
-               bram_dat_w,
                csrbrg_dat_r,
-               csrbrg_dat_w,
-               isp1362_dat_r,
-               isp1362_dat_w;
+               csrbrg_dat_w;
 
-wire [3:0]     brg_sel,
-               bram_sel;
+wire [3:0]     brg_sel;
 
 wire           brg_we,
-               bram_we,
-               csrbrg_we,
-               isp1362_we;
+               csrbrg_we;
 
 wire           brg_cyc,
                norflash_cyc,
-               bram_cyc,
-               csrbrg_cyc,
-               isp1362_cyc;
+               csrbrg_cyc;
 
 wire           brg_stb,
                norflash_stb,
-               bram_stb,
-               csrbrg_stb,
-               isp1362_stb;
+               csrbrg_stb;
 
 wire           brg_ack,
                norflash_ack,
-               bram_ack,
-               csrbrg_ack,
-               isp1362_ack;
+               csrbrg_ack;
 
 //---------------------------------------------------------------------------
 // Wishbone switch
@@ -296,10 +280,10 @@ wire              brg_ack,
 conbus #(
        .s_addr_w(3),
        .s0_addr(3'b000),       // norflash     0x00000000
-       .s1_addr(3'b001),       // bram         0x20000000
+       .s1_addr(3'b001),       // free         0x20000000
        .s2_addr(3'b010),       // FML bridge   0x40000000
        .s3_addr(3'b100),       // CSR bridge   0x80000000
-       .s4_addr(3'b101)        // isp1362      0xa0000000
+       .s4_addr(3'b101)        // free         0xa0000000
 ) conbus (
        .sys_clk(sys_clk),
        .sys_rst(sys_rst),
@@ -362,15 +346,15 @@ conbus #(
        .s0_stb_o(norflash_stb),
        .s0_ack_i(norflash_ack),
        // Slave 1
-       .s1_dat_i(bram_dat_r),
-       .s1_dat_o(bram_dat_w),
-       .s1_adr_o(bram_adr),
-       .s1_cti_o(bram_cti),
-       .s1_sel_o(bram_sel),
-       .s1_we_o(bram_we),
-       .s1_cyc_o(bram_cyc),
-       .s1_stb_o(bram_stb),
-       .s1_ack_i(bram_ack),
+       .s1_dat_i(32'bx),
+       .s1_dat_o(),
+       .s1_adr_o(),
+       .s1_cti_o(),
+       .s1_sel_o(),
+       .s1_we_o(),
+       .s1_cyc_o(),
+       .s1_stb_o(),
+       .s1_ack_i(1'b0),
        // Slave 2
        .s2_dat_i(brg_dat_r),
        .s2_dat_o(brg_dat_w),
@@ -390,13 +374,13 @@ conbus #(
        .s3_stb_o(csrbrg_stb),
        .s3_ack_i(csrbrg_ack),
        // Slave 4
-       .s4_dat_i(isp1362_dat_r),
-       .s4_dat_o(isp1362_dat_w),
-       .s4_adr_o(isp1362_adr),
-       .s4_we_o(isp1362_we),
-       .s4_cyc_o(isp1362_cyc),
-       .s4_stb_o(isp1362_stb),
-       .s4_ack_i(isp1362_ack)
+       .s4_dat_i(32'bx),
+       .s4_dat_o(),
+       .s4_adr_o(),
+       .s4_we_o(),
+       .s4_cyc_o(),
+       .s4_stb_o(),
+       .s4_ack_i(1'b0)
 );
 
 //------------------------------------------------------------------
@@ -658,25 +642,6 @@ assign flash_oe_n = 1'b0;
 assign flash_we_n = 1'b1;
 assign flash_ce = 1'b1;
 
-//---------------------------------------------------------------------------
-// BRAM
-//---------------------------------------------------------------------------
-bram #(
-       .adr_width(12)
-) bram (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .wb_adr_i(bram_adr),
-       .wb_dat_o(bram_dat_r),
-       .wb_dat_i(bram_dat_w),
-       .wb_sel_i(bram_sel),
-       .wb_stb_i(bram_stb),
-       .wb_cyc_i(bram_cyc),
-       .wb_ack_o(bram_ack),
-       .wb_we_i(bram_we)
-);
-
 //---------------------------------------------------------------------------
 // UART
 //---------------------------------------------------------------------------
@@ -761,29 +726,6 @@ gen_capabilities gen_capabilities(
        .capabilities(capabilities)
 );
 
-
-//---------------------------------------------------------------------------
-// USB interface
-//---------------------------------------------------------------------------
-`ifdef ENABLE_ISP1362
-isp1362 isp1362(
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .wb_cyc_i(isp1362_cyc),
-       .wb_stb_i(isp1362_stb),
-       .wb_ack_o(isp1362_ack),
-       .wb_adr_i(isp1362_adr),
-       .wb_dat_i(isp1362_dat_w),
-       .wb_dat_o(isp1362_dat_r),
-       .wb_we_i(isp1362_we),
-       
-);
-`else
-assign isp1362_ack = isp1362_cyc & isp1362_stb;
-assign isp1362_dat_r = 32'habadface;
-`endif
-
 //---------------------------------------------------------------------------
 // DDR SDRAM
 //---------------------------------------------------------------------------
index 9c3ef83..5495862 100644 (file)
@@ -1,4 +1,4 @@
-BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v) $(BOARD_DIR)/../gen_capabilities.v
+BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v) $(BOARD_DIR)/../../gen_capabilities.v
 
 CONBUS_SRC=$(wildcard $(CORES_DIR)/conbus/rtl/*.v)
 LM32_SRC=                                              \
@@ -21,13 +21,43 @@ FMLARB_SRC=$(wildcard $(CORES_DIR)/fmlarb/rtl/*.v)
 FMLBRG_SRC=$(wildcard $(CORES_DIR)/fmlbrg/rtl/*.v)
 CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v)
 NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash8/rtl/*.v)
-BRAM_SRC=$(wildcard $(CORES_DIR)/bram/rtl/*.v)
 UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
 SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/spartan6/*.v)
-VGAFB_SRC=$(wildcard $(CORES_DIR)/vgafb/rtl/*.v)
+VGAFB_SRC=                                             \
+       $(CORES_DIR)/vgafb/rtl/vgafb_graycounter.v      \
+       $(CORES_DIR)/vgafb/rtl/vgafb_asfifo.v           \
+       $(CORES_DIR)/vgafb/rtl/vgafb_pixelfeed.v        \
+       $(CORES_DIR)/vgafb/rtl/vgafb_ctlif.v            \
+       $(CORES_DIR)/vgafb/rtl/vgafb_fifo64to16.v       \
+       $(CORES_DIR)/vgafb/rtl/vgafb.v
 AC97_SRC=$(wildcard $(CORES_DIR)/ac97/rtl/*.v)
 PFPU_SRC=$(wildcard $(CORES_DIR)/pfpu/rtl/*.v)
-TMU_SRC=$(wildcard $(CORES_DIR)/tmu/rtl/*.v)
+TMU_SRC=                                               \
+       $(CORES_DIR)/tmu2/rtl/tmu2_adrgen.v             \
+       $(CORES_DIR)/tmu2/rtl/tmu2_clamp.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_dpram_sw.v           \
+       $(CORES_DIR)/tmu2/rtl/tmu2_hdiv.v               \
+       $(CORES_DIR)/tmu2/rtl/tmu2_burst.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_pixout.v             \
+       $(CORES_DIR)/tmu2/rtl/tmu2.v                    \
+       $(CORES_DIR)/tmu2/rtl/tmu2_ctlif.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_fetchvertex.v        \
+       $(CORES_DIR)/tmu2/rtl/tmu2_hinterp.v            \
+       $(CORES_DIR)/tmu2/rtl/tmu2_qpram32_ss.v         \
+       $(CORES_DIR)/tmu2/rtl/tmu2_vdivops.v            \
+       $(CORES_DIR)/tmu2/rtl/tmu2_decay.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_geninterp18.v        \
+       $(CORES_DIR)/tmu2/rtl/tmu2_mask.v               \
+       $(CORES_DIR)/tmu2/rtl/tmu2_qpram.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_vdiv.v               \
+       $(CORES_DIR)/tmu2/rtl/tmu2_divider17.v          \
+       $(CORES_DIR)/tmu2/rtl/tmu2_hdivops.v            \
+       $(CORES_DIR)/tmu2/rtl/tmu2_texcache.v           \
+       $(CORES_DIR)/tmu2/rtl/tmu2_vinterp.v            \
+       $(CORES_DIR)/tmu2/rtl/tmu2_blend.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_mult2_virtex4.v      \
+       $(CORES_DIR)/tmu2/rtl/tmu2_fdest.v              \
+       $(CORES_DIR)/tmu2/rtl/tmu2_alpha.v
 
-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC)
+CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC)
index 1cb9657..3ced6c1 100644 (file)
@@ -249,46 +249,37 @@ wire              cpuibus_ack,
 //------------------------------------------------------------------
 wire [31:0]    brg_adr,
                norflash_adr,
-               bram_adr,
                csrbrg_adr,
                aceusb_adr;
 
-wire [2:0]     brg_cti,
-               bram_cti;
+wire [2:0]     brg_cti;
 
 wire [31:0]    brg_dat_r,
                brg_dat_w,
                norflash_dat_r,
-               bram_dat_r,
-               bram_dat_w,
                csrbrg_dat_r,
                csrbrg_dat_w,
                aceusb_dat_r,
                aceusb_dat_w;
 
-wire [3:0]     brg_sel,
-               bram_sel;
+wire [3:0]     brg_sel;
 
 wire           brg_we,
-               bram_we,
                csrbrg_we,
                aceusb_we;
 
 wire           brg_cyc,
                norflash_cyc,
-               bram_cyc,
                csrbrg_cyc,
                aceusb_cyc;
 
 wire           brg_stb,
                norflash_stb,
-               bram_stb,
                csrbrg_stb,
                aceusb_stb;
 
 wire           brg_ack,
                norflash_ack,
-               bram_ack,
                csrbrg_ack,
                aceusb_ack;
 
@@ -298,7 +289,7 @@ wire                brg_ack,
 conbus #(
        .s_addr_w(3),
        .s0_addr(3'b000),       // norflash     0x00000000
-       .s1_addr(3'b001),       // bram         0x20000000
+       .s1_addr(3'b001),       // free         0x20000000
        .s2_addr(3'b010),       // FML bridge   0x40000000
        .s3_addr(3'b100),       // CSR bridge   0x80000000
        .s4_addr(3'b101)        // aceusb       0xa0000000
@@ -384,15 +375,15 @@ conbus #(
        .s0_stb_o(norflash_stb),
        .s0_ack_i(norflash_ack),
        // Slave 1
-       .s1_dat_i(bram_dat_r),
-       .s1_dat_o(bram_dat_w),
-       .s1_adr_o(bram_adr),
-       .s1_cti_o(bram_cti),
-       .s1_sel_o(bram_sel),
-       .s1_we_o(bram_we),
-       .s1_cyc_o(bram_cyc),
-       .s1_stb_o(bram_stb),
-       .s1_ack_i(bram_ack),
+       .s1_dat_i(32'bx),
+       .s1_dat_o(),
+       .s1_adr_o(),
+       .s1_cti_o(),
+       .s1_sel_o(),
+       .s1_we_o(),
+       .s1_cyc_o(),
+       .s1_stb_o(),
+       .s1_ack_i(1'b0),
        // Slave 2
        .s2_dat_i(brg_dat_r),
        .s2_dat_o(brg_dat_w),
@@ -732,25 +723,6 @@ assign sram_clk = sys_clk;
 assign sram_ce_n = 1'b1;
 assign sram_zz = 1'b1;
 
-//---------------------------------------------------------------------------
-// BRAM
-//---------------------------------------------------------------------------
-bram #(
-       .adr_width(12)
-) bram (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .wb_adr_i(bram_adr),
-       .wb_dat_o(bram_dat_r),
-       .wb_dat_i(bram_dat_w),
-       .wb_sel_i(bram_sel),
-       .wb_stb_i(bram_stb),
-       .wb_cyc_i(bram_cyc),
-       .wb_ack_o(bram_ack),
-       .wb_we_i(bram_we)
-);
-
 //---------------------------------------------------------------------------
 // UART
 //---------------------------------------------------------------------------
index 86515c0..fce8739 100644 (file)
@@ -21,7 +21,6 @@ FMLARB_SRC=$(wildcard $(CORES_DIR)/fmlarb/rtl/*.v)
 FMLBRG_SRC=$(wildcard $(CORES_DIR)/fmlbrg/rtl/*.v)
 CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v)
 NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash32/rtl/*.v)
-BRAM_SRC=$(wildcard $(CORES_DIR)/bram/rtl/*.v)
 UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
 SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
 ACEUSB_SRC=$(wildcard $(CORES_DIR)/aceusb/rtl/*.v)
@@ -65,4 +64,4 @@ PS2_SRC=$(wildcard $(CORES_DIR)/ps2/rtl/*.v)
 ETHERNET_SRC=$(wildcard $(CORES_DIR)/minimac/rtl/*.v)
 FMLMETER_SRC=$(wildcard $(CORES_DIR)/fmlmeter/rtl/*.v)
 
-CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(BRAM_SRC) $(UART_SRC) $(SYSCTL_SRC) $(ACEUSB_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(PS2_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
+CORES_SRC=$(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(ACEUSB_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(PS2_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
index a7537ad..26048f1 100755 (executable)
@@ -6,6 +6,7 @@ source $BASEDIR/coredoc.inc
 
 cd $BASEDIR/tools && make clean
 
+cd $BASEDIR/software/libhpdmc && make clean
 cd $BASEDIR/software/libbase && make clean
 cd $BASEDIR/software/libmath && make clean
 cd $BASEDIR/software/libhal && make clean
diff --git a/cores/bram/doc/Makefile b/cores/bram/doc/Makefile
deleted file mode 100644 (file)
index 73f0e1b..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-TEX=bram.tex
-
-DVI=$(TEX:.tex=.dvi)
-PS=$(TEX:.tex=.ps)
-PDF=$(TEX:.tex=.pdf)
-AUX=$(TEX:.tex=.aux)
-LOG=$(TEX:.tex=.log)
-
-all: $(PDF)
-
-%.dvi: %.tex
-       latex $<
-
-%.ps: %.dvi
-       dvips $<
-
-%.pdf: %.ps
-       ps2pdf $<
-
-clean:
-       rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
-
-.PHONY: clean
diff --git a/cores/bram/doc/bram.tex b/cores/bram/doc/bram.tex
deleted file mode 100644 (file)
index ae8ae70..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-\documentclass[a4paper,11pt]{article}
-\usepackage{fullpage}
-\usepackage[latin1]{inputenc}
-\usepackage[T1]{fontenc}
-\usepackage[normalem]{ulem}
-\usepackage[english]{babel}
-\usepackage{listings,babel}
-\lstset{breaklines=true,basicstyle=\ttfamily}
-\usepackage{graphicx}
-\usepackage{moreverb}
-\usepackage{url}
-
-\title{Wishbone Block RAM}
-\author{S\'ebastien Bourdeauducq}
-\date{December 2009}
-\begin{document}
-\setlength{\parindent}{0pt}
-\setlength{\parskip}{5pt}
-\maketitle{}
-\section{Specifications}
-This core creates 32-bit storage RAM on the Wishbone bus by using FPGA Block RAM.
-
-Byte-wide writes are supported. Burst access is not supported.
-
-The typical use case is to provide initial memory for softcore CPUs.
-
-\section{Using the core}
-You should specify the block RAM storage depth, in bytes, by using the \verb!adr_width! parameter.
-
-\section*{Copyright notice}
-Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
-Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
-
-\end{document}
diff --git a/cores/bram/rtl/bram.v b/cores/bram/rtl/bram.v
deleted file mode 100644 (file)
index 894bbd2..0000000
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module bram #(
-       parameter adr_width = 11 // in bytes
-) (
-       input sys_clk,
-       input sys_rst,
-
-       input wb_stb_i,
-       input wb_cyc_i,
-       input wb_we_i,
-       output reg wb_ack_o,
-       input [31:0] wb_adr_i,
-       output [31:0] wb_dat_o,
-       input [31:0] wb_dat_i,
-       input [3:0] wb_sel_i
-);
-
-//-----------------------------------------------------------------
-// Storage depth in 32 bit words
-//-----------------------------------------------------------------
-parameter word_width = adr_width - 2;
-parameter word_depth = (1 << word_width);
-
-
-//-----------------------------------------------------------------
-// Actual RAM
-//-----------------------------------------------------------------
-reg [7:0] ram0 [0:word_depth-1];
-reg [7:0] ram1 [0:word_depth-1];
-reg [7:0] ram2 [0:word_depth-1];
-reg [7:0] ram3 [0:word_depth-1];
-wire [word_width-1:0] adr;
-
-wire [7:0] ram0di;
-wire ram0we;
-wire [7:0] ram1di;
-wire ram1we;
-wire [7:0] ram2di;
-wire ram2we;
-wire [7:0] ram3di;
-wire ram3we;
-
-reg [7:0] ram0do;
-reg [7:0] ram1do;
-reg [7:0] ram2do;
-reg [7:0] ram3do;
-
-always @(posedge sys_clk) begin
-       if(ram0we)
-               ram0[adr] <= ram0di;
-       ram0do <= ram0[adr];
-end
-
-always @(posedge sys_clk) begin
-       if(ram1we)
-               ram1[adr] <= ram1di;
-       ram1do <= ram1[adr];
-end
-
-always @(posedge sys_clk) begin
-       if(ram2we)
-               ram2[adr] <= ram2di;
-       ram2do <= ram2[adr];
-end
-
-always @(posedge sys_clk) begin
-       if(ram3we)
-               ram3[adr] <= ram3di;
-       ram3do <= ram3[adr];
-end
-
-assign ram0we = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[0];
-assign ram1we = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[1];
-assign ram2we = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[2];
-assign ram3we = wb_cyc_i & wb_stb_i & wb_we_i & wb_sel_i[3];
-
-assign ram0di = wb_dat_i[7:0];
-assign ram1di = wb_dat_i[15:8];
-assign ram2di = wb_dat_i[23:16];
-assign ram3di = wb_dat_i[31:24];
-
-assign wb_dat_o = {ram3do, ram2do, ram1do, ram0do};
-
-assign adr = wb_adr_i[adr_width-1:2];
-
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               wb_ack_o <= 1'b0;
-       else begin
-               if(wb_cyc_i & wb_stb_i)
-                       wb_ack_o <= ~wb_ack_o;
-               else
-                       wb_ack_o <= 1'b0;
-       end
-end
-
-endmodule
index 3073da3..7c06eec 100644 (file)
@@ -159,6 +159,8 @@ tmu2_qpram #(
 
 /* HIT HANDLING */
 
+reg flush_mode;
+
 reg access_requested;
 always @(posedge sys_clk) begin
        if(sys_rst)
@@ -200,7 +202,7 @@ wire hit_c = ignore_c | (~tagmem_we_r & valid_c & (tag_c == tadrc8_r[fml_depth-1
 wire hit_d = ignore_d | (~tagmem_we_r & valid_d & (tag_d == tadrd8_r[fml_depth-1:cache_depth]));
 
 assign pipe_stb_o = access_requested & hit_a & hit_b & hit_c & hit_d;
-assign pipe_ack_o = (pipe_ack_i & pipe_stb_o) | ~access_requested;
+assign pipe_ack_o = ~flush_mode & ((pipe_ack_i & pipe_stb_o) | ~access_requested);
 
 assign retry = ~pipe_ack_o;
 
@@ -327,7 +329,6 @@ always @(posedge sys_clk) begin
 end
 
 wire flush_done;
-reg flush_mode;
 reg [cache_depth-1-5:0] flush_counter;
 always @(posedge sys_clk) begin
        if(flush_mode)
index b639ef8..dfdd21d 100644 (file)
@@ -63,11 +63,6 @@ Mico32 from Lattice Semiconductor has been chosen for this purpose. It can run a
 \subsubsection{NOR flash}
 The Milkymist BIOS is stored in an external NOR flash chip. The NOR flash controller in Milkymist has been designed to prioritize hardware simplicity over performance and functionality. It only supports reading from the flash; storing the boot image must be done using another tool.
 
-\subsubsection{On-chip SRAM}
-The SoC is equipped with a 4KB on-chip RAM, which is mainly used for the initial execution environment, before SDRAM is initialized and functional.
-
-The choice has been made to include this on-chip RAM so that advanced debug programs that do not rely on SDRAM can easily be developed and run. Those programs are very useful for debugging the SDRAM, which is often prone to problems.
-
 \subsubsection{SDRAM}
 For large volatile data storage, Milkymist is designed to use affordable and industry-standard DDR SDRAM chips. A custom memory controller (HPDMC) has been designed as part of the project, as all other free cores were either non-functional or slow.
 
@@ -182,8 +177,6 @@ A minimal Ethernet 10/100 MAC is provided, which connects to MII PHYs.
 \hline
 0x00000000 & Yes & Boot ROM (NOR Flash) \\
 \hline
-0x20000000 & Yes & On-chip SRAM \\
-\hline
 0x40000000 & Yes & \textit{FastMemoryLink bridge} \\
 \hline
 \hspace{5mm} 0x40000000 & Yes & \hspace{5mm} DDR SDRAM data \\