Removed ML401 support
authorlekernel <sebastien.bourdeauducq@lekernel.net>
Wed, 23 Jun 2010 22:06:07 +0000 (00:06 +0200)
committerlekernel <sebastien.bourdeauducq@lekernel.net>
Wed, 23 Jun 2010 22:06:07 +0000 (00:06 +0200)
56 files changed:
boards/gen_capabilities.v
boards/milkymist-one/flash/Makefile
boards/milkymist-one/rtl/system.v
boards/xilinx-ml401/rtl/ddram.v [deleted file]
boards/xilinx-ml401/rtl/lm32_include.v [deleted file]
boards/xilinx-ml401/rtl/setup.v [deleted file]
boards/xilinx-ml401/rtl/system.v [deleted file]
boards/xilinx-ml401/rtl/vga.v [deleted file]
boards/xilinx-ml401/sources.mak [deleted file]
boards/xilinx-ml401/synthesis/Makefile.precision [deleted file]
boards/xilinx-ml401/synthesis/Makefile.synplify [deleted file]
boards/xilinx-ml401/synthesis/Makefile.xst [deleted file]
boards/xilinx-ml401/synthesis/build/.keep_me [deleted file]
boards/xilinx-ml401/synthesis/common.mak [deleted file]
boards/xilinx-ml401/synthesis/common.ucf [deleted file]
boards/xilinx-ml401/synthesis/flash.cmd [deleted file]
boards/xilinx-ml401/synthesis/ioffs.sdc [deleted file]
boards/xilinx-ml401/synthesis/load.cmd [deleted file]
boards/xilinx-ml401/synthesis/precision.tcl [deleted file]
boards/xilinx-ml401/synthesis/precision.ucf [deleted file]
boards/xilinx-ml401/synthesis/synplify.prj [deleted file]
boards/xilinx-ml401/synthesis/synplify.ucf [deleted file]
boards/xilinx-ml401/synthesis/system.xst [deleted file]
boards/xilinx-ml401/synthesis/xst.ucf [deleted file]
boards/xilinx-ml401/test/Makefile [deleted file]
boards/xilinx-ml401/test/system_tb.v [deleted file]
clean_all.sh
coredoc.inc
cores/aceusb/doc/Makefile [deleted file]
cores/aceusb/doc/aceusb.tex [deleted file]
cores/aceusb/doc/ds080.pdf [deleted file]
cores/aceusb/rtl/aceusb.v [deleted file]
cores/aceusb/rtl/aceusb_access.v [deleted file]
cores/aceusb/rtl/aceusb_sync.v [deleted file]
cores/aceusb/test/Makefile [deleted file]
cores/aceusb/test/tb_aceusb.v [deleted file]
cores/ps2/rtl/ps2.v [deleted file]
software/bios/Makefile
software/bios/boot.c
software/bios/main.c
software/demo/Makefile
software/demo/shell.c
software/include/base/board.h
software/include/base/cfcard.h [deleted file]
software/include/base/cffat.h [deleted file]
software/include/base/fatfs.h [new file with mode: 0644]
software/include/hw/capabilities.h
software/include/hw/gpio.h
software/include/hw/interrupts.h
software/include/hw/systemace.h [deleted file]
software/libbase/Makefile
software/libbase/board.c
software/libbase/cfcard.c [deleted file]
software/libbase/cffat.c [deleted file]
software/libbase/fatfs.c [new file with mode: 0644]
software/libhpdmc/libhpdmc.S

index b8f53bf..d22e74b 100644 (file)
@@ -21,31 +21,27 @@ module gen_capabilities(
        output [31:0] capabilities
 );
 
-wire systemace;
+wire memorycard;
 wire ac97;
 wire pfpu;
 wire tmu;
-wire ps2_keyboard;
-wire ps2_mouse;
 wire ethernet;
 wire fmlmeter;
 
 assign capabilities = {
-       24'd0,
+       26'd0,
        fmlmeter,
        ethernet,
-       ps2_mouse,
-       ps2_keyboard,
        tmu,
        pfpu,
        ac97,
- systemace
+       memorycard
 };
 
-`ifdef ENABLE_ACEUSB
-assign systemace = 1'b1;
+`ifdef ENABLE_MEMORYCARD
+assign memorycard = 1'b1;
 `else
-assign systemace = 1'b0;
+assign memorycard = 1'b0;
 `endif
 
 `ifdef ENABLE_AC97
@@ -66,18 +62,6 @@ assign tmu = 1'b1;
 assign tmu = 1'b0;
 `endif
 
-`ifdef ENABLE_PS2_KEYBOARD
-assign ps2_keyboard = 1'b1;
-`else
-assign ps2_keyboard = 1'b0;
-`endif
-
-`ifdef ENABLE_PS2_MOUSE
-assign ps2_mouse = 1'b1;
-`else
-assign ps2_mouse = 1'b0;
-`endif
-
 `ifdef ENABLE_ETHERNET
 assign ethernet = 1'b1;
 `else
index 9cf91a0..95acacd 100644 (file)
@@ -2,7 +2,7 @@ all: flash.mcs
 
 flash.mcs:
        make -C ../../../software/bios
-       srec_cat -Output flash.mcs -Intel ../../../software/bios/bios.bin -Binary
+       srec_cat -Output flash.mcs -Intel ../../../software/bios/bios_splash.bin -Binary
 
 # Run the Xilinx crapware in a separate directory that we can simply rm -rf
 # to get rid of the garbage it puts all over the filesystem.
index cb22386..9f2a38a 100644 (file)
@@ -661,11 +661,9 @@ wire ethernetrx_irq;
 wire ethernettx_irq;
 
 wire [31:0] cpu_interrupt;
-assign cpu_interrupt = {17'd0,
+assign cpu_interrupt = {19'd0,
        ethernettx_irq,
        ethernetrx_irq,
-       1'b0, /* was: mouse */
-       1'b0, /* was: keyboard */
        tmu_irq,
        pfpu_irq,
        ac97dmaw_irq,
diff --git a/boards/xilinx-ml401/rtl/ddram.v b/boards/xilinx-ml401/rtl/ddram.v
deleted file mode 100644 (file)
index a20da34..0000000
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`include "setup.v"
-
-module ddram #(
-       parameter csr_addr = 4'h0
-) (
-       input sys_clk,
-       input sys_rst,
-       
-       /* Configuration interface */
-       input [13:0] csr_a,
-       input csr_we,
-       input [31:0] csr_di,
-       output [31:0] csr_do,
-       
-       /* FML 4x64 interface */
-       input [`SDRAM_DEPTH-1:0] fml_adr,
-       input fml_stb,
-       input fml_we,
-       output fml_ack,
-       input [7:0] fml_sel,
-       input [63:0] fml_di,
-       output [63:0] fml_do,
-       
-       /* DDRAM pads */
-       output sdram_clk_p,
-       output sdram_clk_n,
-       input sdram_clk_fb,
-       output sdram_cke,
-       output sdram_cs_n,
-       output sdram_we_n,
-       output sdram_cas_n,
-       output sdram_ras_n,
-       output [12:0] sdram_adr,
-       output [1:0] sdram_ba,
-       output [3:0] sdram_dqm,
-       inout [31:0] sdram_dq,
-       inout [3:0] sdram_dqs
-);
-
-`ifndef SIMULATION
-wire dqs_clk;
-wire idelay_clk;
-wire idelay_clk_buffered;
-wire locked1;
-DCM_PS #(
-       .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-
-       .CLKFX_DIVIDE(3),               // 1 to 32
-       .CLKFX_MULTIPLY(2),             // 2 to 32
-       
-       .CLKIN_DIVIDE_BY_2("FALSE"),
-       .CLKIN_PERIOD(`CLOCK_PERIOD),
-       .CLKOUT_PHASE_SHIFT("NONE"),
-       .CLK_FEEDBACK("1X"),
-       .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
-       .DFS_FREQUENCY_MODE("LOW"),
-       .DLL_FREQUENCY_MODE("LOW"),
-       .DUTY_CYCLE_CORRECTION("TRUE"),
-       .FACTORY_JF(16'hF0F0),
-       .PHASE_SHIFT(0),
-       .STARTUP_WAIT("FALSE")
-) clkgen_sdram (
-       .CLK0(sdram_clk_p),
-       .CLK90(),
-       .CLK180(sdram_clk_n),
-       .CLK270(),
-
-       .CLK2X(idelay_clk),
-       .CLK2X180(),
-
-       .CLKDV(),
-       .CLKFX(),
-       .CLKFX180(),
-       .LOCKED(locked1),
-       .CLKFB(sdram_clk_fb),
-       .CLKIN(sys_clk),
-       .RST(1'b0)
-);
-
-wire psen;
-wire psincdec;
-wire psdone;
-wire locked2;
-DCM_PS #(
-       .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
-
-       .CLKFX_DIVIDE(3),               // 1 to 32
-       .CLKFX_MULTIPLY(2),             // 2 to 32
-       
-       .CLKIN_DIVIDE_BY_2("FALSE"),
-       .CLKIN_PERIOD(`CLOCK_PERIOD),
-       .CLKOUT_PHASE_SHIFT("VARIABLE_POSITIVE"),
-       .CLK_FEEDBACK("1X"),
-       .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
-       .DFS_FREQUENCY_MODE("LOW"),
-       .DLL_FREQUENCY_MODE("LOW"),
-       .DUTY_CYCLE_CORRECTION("TRUE"),
-       .FACTORY_JF(16'hF0F0),
-       .PHASE_SHIFT(0),
-       .STARTUP_WAIT("FALSE")
-) clkgen_dqs (
-       .CLK0(dqs_clk),
-       .CLK90(),
-       .CLK180(),
-       .CLK270(),
-
-       .CLK2X(),
-       .CLK2X180(),
-
-       .CLKDV(),
-       .CLKFX(),
-       .CLKFX180(),
-       .LOCKED(locked2),
-       .CLKFB(dqs_clk),
-       .CLKIN(sys_clk),
-       .RST(sys_rst),
-       
-       .PSEN(psen),
-       .PSINCDEC(psincdec),
-       .PSDONE(psdone),
-       .PSCLK(sys_clk)
-);
-
-BUFG idelay_clk_buffer(
-       .I(idelay_clk),
-       .O(idelay_clk_buffered)
-);
-
-IDELAYCTRL idelay_calibration(
-       .RDY(),
-       .REFCLK(idelay_clk_buffered),
-       .RST(1'b0)
-);
-`else
-reg dqs_clk;
-assign sdram_clk_p = sys_clk;
-assign sdram_clk_n = ~sys_clk;
-always @(sys_clk) #2.5 dqs_clk <= sys_clk;
-wire locked1 = 1'b1;
-wire locked2 = 1'b1;
-`endif
-
-hpdmc #(
-       .csr_addr(csr_addr),
-       .sdram_depth(`SDRAM_DEPTH),
-       .sdram_columndepth(`SDRAM_COLUMNDEPTH)
-) hpdmc (
-       .sys_clk(sys_clk),
-       .sys_clk_n(1'b0), /* < not needed on Virtex-4 */
-       .dqs_clk(dqs_clk),
-       .dqs_clk_n(1'b0), /* < not needed on Virtex-4 */
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_di),
-       .csr_do(csr_do),
-       
-       .fml_adr(fml_adr),
-       .fml_stb(fml_stb),
-       .fml_we(fml_we),
-       .fml_ack(fml_ack),
-       .fml_sel(fml_sel),
-       .fml_di(fml_di),
-       .fml_do(fml_do),
-       
-       .sdram_cke(sdram_cke),
-       .sdram_cs_n(sdram_cs_n),
-       .sdram_we_n(sdram_we_n),
-       .sdram_cas_n(sdram_cas_n),
-       .sdram_ras_n(sdram_ras_n),
-       .sdram_dqm(sdram_dqm),
-       .sdram_adr(sdram_adr),
-       .sdram_ba(sdram_ba),
-       .sdram_dq(sdram_dq),
-       .sdram_dqs(sdram_dqs),
-       
-       .dqs_psen(psen),
-       .dqs_psincdec(psincdec),
-       .dqs_psdone(psdone),
-
-       .pll_stat({locked2, locked1})
-);
-
-endmodule
diff --git a/boards/xilinx-ml401/rtl/lm32_include.v b/boards/xilinx-ml401/rtl/lm32_include.v
deleted file mode 100644 (file)
index 6eb448b..0000000
+++ /dev/null
@@ -1,359 +0,0 @@
-// =============================================================================
-//                           COPYRIGHT NOTICE
-// Copyright 2006 (c) Lattice Semiconductor Corporation
-// ALL RIGHTS RESERVED
-// This confidential and proprietary software may be used only as authorised by
-// a licensing agreement from Lattice Semiconductor Corporation.
-// The entire notice above must be reproduced on all authorized copies and
-// copies may only be made to the extent permitted by a licensing agreement from
-// Lattice Semiconductor Corporation.
-//
-// Lattice Semiconductor Corporation        TEL : 1-800-Lattice (USA and Canada)
-// 5555 NE Moore Court                            408-826-6000 (other locations)
-// Hillsboro, OR 97124                     web  : http://www.latticesemi.com/
-// U.S.A                                   email: techsupport@latticesemi.com
-// =============================================================================/
-//                         FILE DETAILS
-// Project          : LatticeMico32
-// File             : lm32_include.v
-// Title            : CPU global macros
-// Version          : 6.1.17
-//                  : Initial Release
-// Version          : 7.0SP2, 3.0
-//                  : No Change
-// Version          : 3.1
-//                  : No Change
-// Version          : 3.2
-//                  : No Change
-// Version          : 3.3
-//                  : Support for extended configuration register
-// =============================================================================
-
-`ifdef LM32_INCLUDE_V
-`else
-`define LM32_INCLUDE_V
-
-//
-// Common configuration options
-//
-
-`define CFG_EBA_RESET 32'h0
-`define CFG_DEBA_RESET 32'h0
-
-`define CFG_PL_MULTIPLY_ENABLED
-`define CFG_PL_BARREL_SHIFT_ENABLED
-`define CFG_SIGN_EXTEND_ENABLED
-`define CFG_MC_DIVIDE_ENABLED
-
-// Bug in Mico32/Xst ?
-// CFG_ICACHE_ASSOCIATIVITY=2 => works fine
-// CFG_ICACHE_ASSOCIATIVITY=1 => disaster
-// TODO: try with the expensive synthesizers
-`define CFG_ICACHE_ENABLED
-`define CFG_ICACHE_ASSOCIATIVITY   2
-`define CFG_ICACHE_SETS            512
-`define CFG_ICACHE_BYTES_PER_LINE  16
-`define CFG_ICACHE_BASE_ADDRESS    32'h0
-`define CFG_ICACHE_LIMIT           32'h7fffffff
-
-`define CFG_DCACHE_ENABLED
-`define CFG_DCACHE_ASSOCIATIVITY   2
-`define CFG_DCACHE_SETS            512
-`define CFG_DCACHE_BYTES_PER_LINE  16
-`define CFG_DCACHE_BASE_ADDRESS    32'h0
-`define CFG_DCACHE_LIMIT           32'h7fffffff
-
-//
-// End of common configuration options
-//
-
-`ifdef TRUE
-`else
-`define TRUE    1'b1
-`define FALSE   1'b0
-`define TRUE_N  1'b0
-`define FALSE_N 1'b1
-`endif
-
-// Wishbone configuration
-`define CFG_IWB_ENABLED
-`define CFG_DWB_ENABLED
-
-// Data-path width
-`define LM32_WORD_WIDTH                 32
-`define LM32_WORD_RNG                   (`LM32_WORD_WIDTH-1):0
-`define LM32_SHIFT_WIDTH                5
-`define LM32_SHIFT_RNG                  (`LM32_SHIFT_WIDTH-1):0
-`define LM32_BYTE_SELECT_WIDTH          4
-`define LM32_BYTE_SELECT_RNG            (`LM32_BYTE_SELECT_WIDTH-1):0
-
-// Register file size
-`define LM32_REGISTERS                  32
-`define LM32_REG_IDX_WIDTH              5
-`define LM32_REG_IDX_RNG                (`LM32_REG_IDX_WIDTH-1):0
-
-// Standard register numbers
-`define LM32_RA_REG                     `LM32_REG_IDX_WIDTH'd29
-`define LM32_EA_REG                     `LM32_REG_IDX_WIDTH'd30
-`define LM32_BA_REG                     `LM32_REG_IDX_WIDTH'd31
-
-// Range of Program Counter. Two LSBs are always 0. 
-// `ifdef CFG_ICACHE_ENABLED
-// `define LM32_PC_WIDTH                   (clogb2(`CFG_ICACHE_LIMIT-`CFG_ICACHE_BASE_ADDRESS)-2)
-// `else
-// `ifdef CFG_IWB_ENABLED
-`define LM32_PC_WIDTH                   (`LM32_WORD_WIDTH-2)
-// `else
-// `define LM32_PC_WIDTH                   `LM32_IROM_ADDRESS_WIDTH
-// `endif
-// `endif
-`define LM32_PC_RNG                     (`LM32_PC_WIDTH+2-1):2
-
-// Range of an instruction
-`define LM32_INSTRUCTION_WIDTH          32
-`define LM32_INSTRUCTION_RNG            (`LM32_INSTRUCTION_WIDTH-1):0
-
-// Adder operation
-`define LM32_ADDER_OP_ADD               1'b0
-`define LM32_ADDER_OP_SUBTRACT          1'b1
-
-// Shift direction
-`define LM32_SHIFT_OP_RIGHT             1'b0
-`define LM32_SHIFT_OP_LEFT              1'b1
-
-// Currently always enabled
-`define CFG_BUS_ERRORS_ENABLED
-
-// Derive macro that indicates whether we have single-stepping or not
-`ifdef CFG_ROM_DEBUG_ENABLED
-`define LM32_SINGLE_STEP_ENABLED
-`else
-`ifdef CFG_HW_DEBUG_ENABLED
-`define LM32_SINGLE_STEP_ENABLED
-`endif
-`endif
-
-// Derive macro that indicates whether JTAG interface is required
-`ifdef CFG_JTAG_UART_ENABLED
-`define LM32_JTAG_ENABLED
-`else
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_JTAG_ENABLED
-`else
-`endif
-`endif
-
-// Derive macro that indicates whether we have a barrel-shifter or not
-`ifdef CFG_PL_BARREL_SHIFT_ENABLED
-`define LM32_BARREL_SHIFT_ENABLED
-`else // CFG_PL_BARREL_SHIFT_ENABLED
-`ifdef CFG_MC_BARREL_SHIFT_ENABLED
-`define LM32_BARREL_SHIFT_ENABLED
-`else
-`define LM32_NO_BARREL_SHIFT
-`endif
-`endif // CFG_PL_BARREL_SHIFT_ENABLED
-
-// Derive macro that indicates whether we have a multiplier or not
-`ifdef CFG_PL_MULTIPLY_ENABLED
-`define LM32_MULTIPLY_ENABLED
-`else
-`ifdef CFG_MC_MULTIPLY_ENABLED
-`define LM32_MULTIPLY_ENABLED
-`endif
-`endif
-
-// Derive a macro that indicates whether or not the multi-cycle arithmetic unit is required
-`ifdef CFG_MC_DIVIDE_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-`ifdef CFG_MC_MULTIPLY_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-`ifdef CFG_MC_BARREL_SHIFT_ENABLED
-`define LM32_MC_ARITHMETIC_ENABLED
-`endif
-
-// Derive macro that indicates if we are using an EBR register file
-`ifdef CFG_EBR_POSEDGE_REGISTER_FILE
-`define LM32_EBR_REGISTER_FILE
-`endif
-`ifdef CFG_EBR_NEGEDGE_REGISTER_FILE
-`define LM32_EBR_REGISTER_FILE
-`endif
-
-// Revision number
-`define LM32_REVISION                   6'h02
-
-// Logical operations - Function encoded directly in instruction
-`define LM32_LOGIC_OP_RNG               3:0
-
-// Conditions for conditional branches
-`define LM32_CONDITION_WIDTH            3
-`define LM32_CONDITION_RNG              (`LM32_CONDITION_WIDTH-1):0
-`define LM32_CONDITION_E                3'b001
-`define LM32_CONDITION_G                3'b010
-`define LM32_CONDITION_GE               3'b011
-`define LM32_CONDITION_GEU              3'b100
-`define LM32_CONDITION_GU               3'b101
-`define LM32_CONDITION_NE               3'b111
-`define LM32_CONDITION_U1               3'b000
-`define LM32_CONDITION_U2               3'b110
-
-// Size of load or store instruction - Encoding corresponds to opcode
-`define LM32_SIZE_WIDTH                 2
-`define LM32_SIZE_RNG                   1:0
-`define LM32_SIZE_BYTE                  2'b00
-`define LM32_SIZE_HWORD                 2'b11
-`define LM32_SIZE_WORD                  2'b10
-`define LM32_ADDRESS_LSBS_WIDTH         2
-
-// Width and range of a CSR index
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_WIDTH                  5
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`else
-`ifdef CFG_JTAG_ENABLED
-`define LM32_CSR_WIDTH                  4
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`else
-`define LM32_CSR_WIDTH                  3
-`define LM32_CSR_RNG                    (`LM32_CSR_WIDTH-1):0
-`endif
-`endif
-
-// CSR indices
-`define LM32_CSR_IE                     `LM32_CSR_WIDTH'h0
-`define LM32_CSR_IM                     `LM32_CSR_WIDTH'h1
-`define LM32_CSR_IP                     `LM32_CSR_WIDTH'h2
-`define LM32_CSR_ICC                    `LM32_CSR_WIDTH'h3
-`define LM32_CSR_DCC                    `LM32_CSR_WIDTH'h4
-`define LM32_CSR_CC                     `LM32_CSR_WIDTH'h5
-`define LM32_CSR_CFG                    `LM32_CSR_WIDTH'h6
-`define LM32_CSR_EBA                    `LM32_CSR_WIDTH'h7
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_DC                     `LM32_CSR_WIDTH'h8
-`define LM32_CSR_DEBA                   `LM32_CSR_WIDTH'h9
-`endif
-`define LM32_CSR_CFG2                   `LM32_CSR_WIDTH'ha
-`ifdef CFG_JTAG_ENABLED
-`define LM32_CSR_JTX                    `LM32_CSR_WIDTH'he
-`define LM32_CSR_JRX                    `LM32_CSR_WIDTH'hf
-`endif
-`ifdef CFG_DEBUG_ENABLED
-`define LM32_CSR_BP0                    `LM32_CSR_WIDTH'h10
-`define LM32_CSR_BP1                    `LM32_CSR_WIDTH'h11
-`define LM32_CSR_BP2                    `LM32_CSR_WIDTH'h12
-`define LM32_CSR_BP3                    `LM32_CSR_WIDTH'h13
-`define LM32_CSR_WP0                    `LM32_CSR_WIDTH'h18
-`define LM32_CSR_WP1                    `LM32_CSR_WIDTH'h19
-`define LM32_CSR_WP2                    `LM32_CSR_WIDTH'h1a
-`define LM32_CSR_WP3                    `LM32_CSR_WIDTH'h1b
-`endif 
-
-// Values for WPC CSR
-`define LM32_WPC_C_RNG                  1:0
-`define LM32_WPC_C_DISABLED             2'b00
-`define LM32_WPC_C_READ                 2'b01
-`define LM32_WPC_C_WRITE                2'b10
-`define LM32_WPC_C_READ_WRITE           2'b11
-
-// Exception IDs
-`define LM32_EID_WIDTH                  3
-`define LM32_EID_RNG                    (`LM32_EID_WIDTH-1):0
-`define LM32_EID_RESET                  3'h0
-`define LM32_EID_BREAKPOINT             3'd1
-`define LM32_EID_INST_BUS_ERROR         3'h2
-`define LM32_EID_WATCHPOINT             3'd3
-`define LM32_EID_DATA_BUS_ERROR         3'h4
-`define LM32_EID_DIVIDE_BY_ZERO         3'h5
-`define LM32_EID_INTERRUPT              3'h6
-`define LM32_EID_SCALL                  3'h7
-
-// Pipeline result selection mux controls
-
-`define LM32_D_RESULT_SEL_0_RNG          0:0
-`define LM32_D_RESULT_SEL_0_REG_0        1'b0
-`define LM32_D_RESULT_SEL_0_NEXT_PC      1'b1
-
-`define LM32_D_RESULT_SEL_1_RNG          1:0
-`define LM32_D_RESULT_SEL_1_ZERO         2'b00
-`define LM32_D_RESULT_SEL_1_REG_1        2'b01
-`define LM32_D_RESULT_SEL_1_IMMEDIATE    2'b10
-
-`define LM32_USER_OPCODE_WIDTH           11
-`define LM32_USER_OPCODE_RNG             (`LM32_USER_OPCODE_WIDTH-1):0
-
-// Derive a macro to indicate if either of the caches are implemented
-`ifdef CFG_ICACHE_ENABLED
-`define LM32_CACHE_ENABLED
-`else
-`ifdef CFG_DCACHE_ENABLED
-`define LM32_CACHE_ENABLED
-`endif
-`endif
-
-/////////////////////////////////////////////////////
-// Interrupts
-/////////////////////////////////////////////////////
-
-// Always enable interrupts
-`define CFG_INTERRUPTS_ENABLED
-
-// Currently this is fixed to 32 and should not be changed
-`define CFG_INTERRUPTS                  32
-`define LM32_INTERRUPT_WIDTH            `CFG_INTERRUPTS
-`define LM32_INTERRUPT_RNG              (`LM32_INTERRUPT_WIDTH-1):0
-
-/////////////////////////////////////////////////////
-// General
-/////////////////////////////////////////////////////
-
-// Sub-word range types
-`define LM32_BYTE_WIDTH                 8
-`define LM32_BYTE_RNG                   7:0
-`define LM32_HWORD_WIDTH                16
-`define LM32_HWORD_RNG                  15:0
-
-// Word sub-byte indicies
-`define LM32_BYTE_0_RNG                  7:0
-`define LM32_BYTE_1_RNG                  15:8
-`define LM32_BYTE_2_RNG                  23:16
-`define LM32_BYTE_3_RNG                  31:24
-
-// Word sub-halfword indices
-`define LM32_HWORD_0_RNG                 15:0
-`define LM32_HWORD_1_RNG                 31:16
-
-// Use a synchronous reset
-`define CFG_RESET_SENSITIVITY
-
-// V.T. Srce
-`define SRCE
-
-// Whether to include context registers for debug exceptions
-// in addition to standard exception handling registers
-// Bizarre - Removing this increases LUT count!
-`define CFG_DEBUG_EXCEPTIONS_ENABLED
-
-// Wishbone defines
-// Refer to Wishbone System-on-Chip Interconnection Architecture
-// These should probably be moved to a Wishbone common file
-
-// Wishbone cycle types
-`define LM32_CTYPE_WIDTH                3
-`define LM32_CTYPE_RNG                  (`LM32_CTYPE_WIDTH-1):0
-`define LM32_CTYPE_CLASSIC              3'b000
-`define LM32_CTYPE_CONSTANT             3'b001
-`define LM32_CTYPE_INCREMENTING         3'b010
-`define LM32_CTYPE_END                  3'b111
-
-// Wishbone burst types
-`define LM32_BTYPE_WIDTH                2
-`define LM32_BTYPE_RNG                  (`LM32_BTYPE_WIDTH-1):0
-`define LM32_BTYPE_LINEAR               2'b00
-`define LM32_BTYPE_4_BEAT               2'b01
-`define LM32_BTYPE_8_BEAT               2'b10
-`define LM32_BTYPE_16_BEAT              2'b11
-
-`endif
diff --git a/boards/xilinx-ml401/rtl/setup.v b/boards/xilinx-ml401/rtl/setup.v
deleted file mode 100644 (file)
index c6e38ad..0000000
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/*
- * Enable or disable some cores.
- * A complete system would have them all except the debug cores
- * but when working on a specific part, it's very useful to be
- * able to cut down synthesis times.
- */
-
-`define ENABLE_ACEUSB
-`define ENABLE_AC97
-`define ENABLE_PFPU
-`define ENABLE_TMU
-`define ENABLE_PS2_KEYBOARD
-`define ENABLE_PS2_MOUSE
-`define ENABLE_ETHERNET
-`define ENABLE_FMLMETER
-
-/*
- * System clock frequency in Hz.
- */
-`define CLOCK_FREQUENCY 100000000
-
-/*
- * System clock period in ns (must be in sync with CLOCK_FREQUENCY).
- */
-`define CLOCK_PERIOD 10
-
-/*
- * Default baudrate for the debug UART.
- */
-`define BAUD_RATE 115200
-
-/*
- * SDRAM depth, in bytes (the number of bits you need to address the whole
- * array with byte granularity)
- */
-`define SDRAM_DEPTH 26
-
-/*
- * SDRAM column depth (the number of column address bits)
- */
-`define SDRAM_COLUMNDEPTH 9
diff --git a/boards/xilinx-ml401/rtl/system.v b/boards/xilinx-ml401/rtl/system.v
deleted file mode 100644 (file)
index 3ced6c1..0000000
+++ /dev/null
@@ -1,1224 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`include "setup.v"
-
-module system(
-       input clkin,
-       input resetin,
-       
-       // Boot ROM
-       output [24:0] flash_adr,
-       input [31:0] flash_d,
-       output flash_byte_n,
-       output flash_oe_n,
-       output flash_we_n,
-       output flash_ce,
-       output flash_ac97_reset_n,
-       
-       output sram_clk,
-       output sram_ce_n,
-       output sram_zz,
-
-       // UART
-       input uart_rxd,
-       output uart_txd,
-
-       // DDR SDRAM
-       output sdram_clk_p,
-       output sdram_clk_n,
-       input sdram_clk_fb,
-       output sdram_cke,
-       output sdram_cs_n,
-       output sdram_we_n,
-       output sdram_cas_n,
-       output sdram_ras_n,
-       output [3:0] sdram_dqm,
-       output [12:0] sdram_adr,
-       output [1:0] sdram_ba,
-       inout [31:0] sdram_dq,
-       inout [3:0] sdram_dqs,
-       
-       // GPIO
-       input [4:0] btn,     // 5
-       output [4:0] btnled, //        5
-       output [3:0] led,    //        2 (2 LEDs for UART activity)
-       input [7:0] dipsw,   // 8
-       output lcd_e,        //        1
-       output lcd_rs,       //        1
-       output lcd_rw,       //        1
-       output [3:0] lcd_d,  //        4
-                            // 13     14
-
-       // VGA
-       output vga_psave_n,
-       output vga_hsync_n,
-       output vga_vsync_n,
-       output vga_sync_n,
-       output vga_blank_n,
-       output [7:0] vga_r,
-       output [7:0] vga_g,
-       output [7:0] vga_b,
-       output vga_clkout,
-       
-       // SystemACE/USB
-       output [6:0] aceusb_a,
-       inout [15:0] aceusb_d,
-       output aceusb_oe_n,
-       output aceusb_we_n,
-       input ace_clkin,
-       output ace_mpce_n,
-       input ace_mpirq,
-       output usb_cs_n,
-       output usb_hpi_reset_n,
-       input usb_hpi_int,
-       
-       // AC97
-       input ac97_clk,
-       input ac97_sin,
-       output ac97_sout,
-       output ac97_sync,
-
-       // PS2
-       inout ps2_clk1,
-       inout ps2_data1,
-       inout ps2_clk2,
-       inout ps2_data2,
-
-       // Ethernet
-       output phy_rst_n,
-       input phy_tx_clk,
-       output [3:0] phy_tx_data,
-       output phy_tx_en,
-       output phy_tx_er,
-       input phy_rx_clk,
-       input [3:0] phy_rx_data,
-       input phy_dv,
-       input phy_rx_er,
-       input phy_col,
-       input phy_crs,
-       output phy_mii_clk,
-       inout phy_mii_data
-);
-
-//------------------------------------------------------------------
-// Clock and Reset Generation
-//------------------------------------------------------------------
-wire sys_clk;
-wire hard_reset;
-
-`ifndef SIMULATION
-BUFG clkbuf(
-       .I(clkin),
-       .O(sys_clk)
-);
-`else
-assign sys_clk = clkin;
-`endif
-
-`ifndef SIMULATION
-/* Synchronize the reset input */
-reg rst0;
-reg rst1;
-always @(posedge sys_clk) rst0 <= resetin;
-always @(posedge sys_clk) rst1 <= rst0;
-
-/* Debounce it (counter holds reset for 10.49ms),
- * and generate power-on reset.
- */
-reg [19:0] rst_debounce;
-reg sys_rst;
-initial rst_debounce <= 20'hFFFFF;
-initial sys_rst <= 1'b1;
-always @(posedge sys_clk) begin
-       if(~rst1 | hard_reset) /* reset pin is active low */
-               rst_debounce <= 20'hFFFFF;
-       else if(rst_debounce != 20'd0)
-               rst_debounce <= rst_debounce - 20'd1;
-       sys_rst <= rst_debounce != 20'd0;
-end
-
-/*
- * We must release the Flash reset before the system reset
- * because the Flash needs some time to come out of reset
- * and the CPU begins fetching instructions from it
- * as soon as the system reset is released.
- * From datasheet, minimum reset pulse width is 100ns
- * and reset-to-read time is 150ns.
- * On the ML401, the reset is combined with the AC97
- * reset, which must be held for 1us.
- * Here we use a 7-bit counter that holds reset
- * for 1.28us and makes everybody happy.
- */
-
-reg [7:0] flash_rstcounter;
-initial flash_rstcounter <= 8'd0;
-always @(posedge sys_clk) begin
-       if(~rst1 & ~sys_rst) /* ~sys_rst is for debouncing */
-               flash_rstcounter <= 8'd0;
-       else if(~flash_rstcounter[7])
-               flash_rstcounter <= flash_rstcounter + 8'd1;
-end
-
-assign flash_ac97_reset_n = flash_rstcounter[7];
-
-wire ac97_rst_n;
-assign ac97_rst_n = flash_rstcounter[7];
-
-/* Just use the same signal for PHY reset */
-assign phy_rst_n = flash_rstcounter[7];
-
-`else
-wire sys_rst;
-assign sys_rst = ~resetin;
-`endif
-
-//------------------------------------------------------------------
-// Wishbone master wires
-//------------------------------------------------------------------
-wire [31:0]    cpuibus_adr,
-               cpudbus_adr,
-               ac97bus_adr,
-               pfpubus_adr,
-               tmumbus_adr,
-               ethernetrxbus_adr,
-               ethernettxbus_adr;
-
-wire [2:0]     cpuibus_cti,
-               cpudbus_cti,
-               ac97bus_cti,
-               tmumbus_cti,
-               ethernetrxbus_cti,
-               ethernettxbus_cti;
-
-wire [31:0]    cpuibus_dat_r,
-               cpudbus_dat_r,
-               cpudbus_dat_w,
-               ac97bus_dat_r,
-               ac97bus_dat_w,
-               pfpubus_dat_w,
-               tmumbus_dat_r,
-               ethernetrxbus_dat_w,
-               ethernettxbus_dat_r;
-
-wire [3:0]     cpudbus_sel;
-
-wire           cpudbus_we,
-               ac97bus_we;
-
-wire           cpuibus_cyc,
-               cpudbus_cyc,
-               ac97bus_cyc,
-               pfpubus_cyc,
-               tmumbus_cyc,
-               ethernetrxbus_cyc,
-               ethernettxbus_cyc;
-
-wire           cpuibus_stb,
-               cpudbus_stb,
-               ac97bus_stb,
-               pfpubus_stb,
-               tmumbus_stb,
-               ethernetrxbus_stb,
-               ethernettxbus_stb;
-
-wire           cpuibus_ack,
-               cpudbus_ack,
-               ac97bus_ack,
-               tmumbus_ack,
-               pfpubus_ack,
-               ethernetrxbus_ack,
-               ethernettxbus_ack;
-
-//------------------------------------------------------------------
-// Wishbone slave wires
-//------------------------------------------------------------------
-wire [31:0]    brg_adr,
-               norflash_adr,
-               csrbrg_adr,
-               aceusb_adr;
-
-wire [2:0]     brg_cti;
-
-wire [31:0]    brg_dat_r,
-               brg_dat_w,
-               norflash_dat_r,
-               csrbrg_dat_r,
-               csrbrg_dat_w,
-               aceusb_dat_r,
-               aceusb_dat_w;
-
-wire [3:0]     brg_sel;
-
-wire           brg_we,
-               csrbrg_we,
-               aceusb_we;
-
-wire           brg_cyc,
-               norflash_cyc,
-               csrbrg_cyc,
-               aceusb_cyc;
-
-wire           brg_stb,
-               norflash_stb,
-               csrbrg_stb,
-               aceusb_stb;
-
-wire           brg_ack,
-               norflash_ack,
-               csrbrg_ack,
-               aceusb_ack;
-
-//---------------------------------------------------------------------------
-// Wishbone switch
-//---------------------------------------------------------------------------
-conbus #(
-       .s_addr_w(3),
-       .s0_addr(3'b000),       // norflash     0x00000000
-       .s1_addr(3'b001),       // free         0x20000000
-       .s2_addr(3'b010),       // FML bridge   0x40000000
-       .s3_addr(3'b100),       // CSR bridge   0x80000000
-       .s4_addr(3'b101)        // aceusb       0xa0000000
-) conbus (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       // Master 0
-       .m0_dat_i(32'hx),
-       .m0_dat_o(cpuibus_dat_r),
-       .m0_adr_i(cpuibus_adr),
-       .m0_cti_i(cpuibus_cti),
-       .m0_we_i(1'b0),
-       .m0_sel_i(4'hf),
-       .m0_cyc_i(cpuibus_cyc),
-       .m0_stb_i(cpuibus_stb),
-       .m0_ack_o(cpuibus_ack),
-       // Master 1
-       .m1_dat_i(cpudbus_dat_w),
-       .m1_dat_o(cpudbus_dat_r),
-       .m1_adr_i(cpudbus_adr),
-       .m1_cti_i(cpudbus_cti),
-       .m1_we_i(cpudbus_we),
-       .m1_sel_i(cpudbus_sel),
-       .m1_cyc_i(cpudbus_cyc),
-       .m1_stb_i(cpudbus_stb),
-       .m1_ack_o(cpudbus_ack),
-       // Master 2
-       .m2_dat_i(ac97bus_dat_w),
-       .m2_dat_o(ac97bus_dat_r),
-       .m2_adr_i(ac97bus_adr),
-       .m2_cti_i(ac97bus_cti),
-       .m2_we_i(ac97bus_we),
-       .m2_sel_i(4'hf),
-       .m2_cyc_i(ac97bus_cyc),
-       .m2_stb_i(ac97bus_stb),
-       .m2_ack_o(ac97bus_ack),
-       // Master 3
-       .m3_dat_i(pfpubus_dat_w),
-       .m3_dat_o(),
-       .m3_adr_i(pfpubus_adr),
-       .m3_cti_i(3'd0),
-       .m3_we_i(1'b1),
-       .m3_sel_i(4'hf),
-       .m3_cyc_i(pfpubus_cyc),
-       .m3_stb_i(pfpubus_stb),
-       .m3_ack_o(pfpubus_ack),
-       // Master 4
-       .m4_dat_i(32'bx),
-       .m4_dat_o(tmumbus_dat_r),
-       .m4_adr_i(tmumbus_adr),
-       .m4_cti_i(tmumbus_cti),
-       .m4_we_i(1'b0),
-       .m4_sel_i(4'hf),
-       .m4_cyc_i(tmumbus_cyc),
-       .m4_stb_i(tmumbus_stb),
-       .m4_ack_o(tmumbus_ack),
-       // Master 5
-       .m5_dat_i(ethernetrxbus_dat_w),
-       .m5_dat_o(),
-       .m5_adr_i(ethernetrxbus_adr),
-       .m5_cti_i(ethernetrxbus_cti),
-       .m5_we_i(1'b1),
-       .m5_sel_i(4'hf),
-       .m5_cyc_i(ethernetrxbus_cyc),
-       .m5_stb_i(ethernetrxbus_stb),
-       .m5_ack_o(ethernetrxbus_ack),
-       // Master 6
-       .m6_dat_i(),
-       .m6_dat_o(ethernettxbus_dat_r),
-       .m6_adr_i(ethernettxbus_adr),
-       .m6_cti_i(ethernettxbus_cti),
-       .m6_we_i(1'b0),
-       .m6_sel_i(4'hf),
-       .m6_cyc_i(ethernettxbus_cyc),
-       .m6_stb_i(ethernettxbus_stb),
-       .m6_ack_o(ethernettxbus_ack),
-
-       // Slave 0
-       .s0_dat_i(norflash_dat_r),
-       .s0_adr_o(norflash_adr),
-       .s0_cyc_o(norflash_cyc),
-       .s0_stb_o(norflash_stb),
-       .s0_ack_i(norflash_ack),
-       // Slave 1
-       .s1_dat_i(32'bx),
-       .s1_dat_o(),
-       .s1_adr_o(),
-       .s1_cti_o(),
-       .s1_sel_o(),
-       .s1_we_o(),
-       .s1_cyc_o(),
-       .s1_stb_o(),
-       .s1_ack_i(1'b0),
-       // Slave 2
-       .s2_dat_i(brg_dat_r),
-       .s2_dat_o(brg_dat_w),
-       .s2_adr_o(brg_adr),
-       .s2_cti_o(brg_cti),
-       .s2_sel_o(brg_sel),
-       .s2_we_o(brg_we),
-       .s2_cyc_o(brg_cyc),
-       .s2_stb_o(brg_stb),
-       .s2_ack_i(brg_ack),
-       // Slave 3
-       .s3_dat_i(csrbrg_dat_r),
-       .s3_dat_o(csrbrg_dat_w),
-       .s3_adr_o(csrbrg_adr),
-       .s3_we_o(csrbrg_we),
-       .s3_cyc_o(csrbrg_cyc),
-       .s3_stb_o(csrbrg_stb),
-       .s3_ack_i(csrbrg_ack),
-       // Slave 4
-       .s4_dat_i(aceusb_dat_r),
-       .s4_dat_o(aceusb_dat_w),
-       .s4_adr_o(aceusb_adr),
-       .s4_we_o(aceusb_we),
-       .s4_cyc_o(aceusb_cyc),
-       .s4_stb_o(aceusb_stb),
-       .s4_ack_i(aceusb_ack)
-);
-
-//------------------------------------------------------------------
-// CSR bus
-//------------------------------------------------------------------
-wire [13:0]    csr_a;
-wire           csr_we;
-wire [31:0]    csr_dw;
-wire [31:0]    csr_dr_uart,
-               csr_dr_sysctl,
-               csr_dr_hpdmc,
-               csr_dr_vga,
-               csr_dr_ac97,
-               csr_dr_pfpu,
-               csr_dr_tmu,
-               csr_dr_ps2,
-               csr_dr_mouse,
-               csr_dr_ethernet,
-               csr_dr_fmlmeter;
-
-//------------------------------------------------------------------
-// FML master wires
-//------------------------------------------------------------------
-wire [`SDRAM_DEPTH-1:0]        fml_brg_adr,
-                       fml_vga_adr,
-                       fml_tmur_adr,
-                       fml_tmudr_adr,
-                       fml_tmuw_adr;
-
-wire                   fml_brg_stb,
-                       fml_vga_stb,
-                       fml_tmur_stb,
-                       fml_tmudr_stb,
-                       fml_tmuw_stb;
-
-wire                   fml_brg_we;
-
-wire                   fml_brg_ack,
-                       fml_vga_ack,
-                       fml_tmur_ack,
-                       fml_tmudr_ack,
-                       fml_tmuw_ack;
-
-wire [7:0]             fml_brg_sel,
-                       fml_tmuw_sel;
-
-wire [63:0]            fml_brg_dw,
-                       fml_tmuw_dw;
-
-wire [63:0]            fml_brg_dr,
-                       fml_vga_dr,
-                       fml_tmur_dr,
-                       fml_tmudr_dr;
-
-//------------------------------------------------------------------
-// FML slave wires, to memory controller
-//------------------------------------------------------------------
-wire [`SDRAM_DEPTH-1:0] fml_adr;
-wire fml_stb;
-wire fml_we;
-wire fml_ack;
-wire [7:0] fml_sel;
-wire [63:0] fml_dw;
-wire [63:0] fml_dr;
-
-//---------------------------------------------------------------------------
-// FML arbiter
-//---------------------------------------------------------------------------
-fmlarb #(
-       .fml_depth(`SDRAM_DEPTH)
-) fmlarb (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       /* VGA framebuffer (high priority) */
-       .m0_adr(fml_vga_adr),
-       .m0_stb(fml_vga_stb),
-       .m0_we(1'b0),
-       .m0_ack(fml_vga_ack),
-       .m0_sel(8'bx),
-       .m0_di(64'bx),
-       .m0_do(fml_vga_dr),
-       
-       /* WISHBONE bridge */
-       .m1_adr(fml_brg_adr),
-       .m1_stb(fml_brg_stb),
-       .m1_we(fml_brg_we),
-       .m1_ack(fml_brg_ack),
-       .m1_sel(fml_brg_sel),
-       .m1_di(fml_brg_dw),
-       .m1_do(fml_brg_dr),
-       
-       /* TMU, pixel read DMA (texture) */
-       .m2_adr(fml_tmur_adr),
-       .m2_stb(fml_tmur_stb),
-       .m2_we(1'b0),
-       .m2_ack(fml_tmur_ack),
-       .m2_sel(8'bx),
-       .m2_di(64'bx),
-       .m2_do(fml_tmur_dr),
-       
-       /* TMU, pixel write DMA */
-       .m3_adr(fml_tmuw_adr),
-       .m3_stb(fml_tmuw_stb),
-       .m3_we(1'b1),
-       .m3_ack(fml_tmuw_ack),
-       .m3_sel(fml_tmuw_sel),
-       .m3_di(fml_tmuw_dw),
-       .m3_do(),
-
-       /* TMU, pixel read DMA (destination) */
-       .m4_adr(fml_tmudr_adr),
-       .m4_stb(fml_tmudr_stb),
-       .m4_we(1'b0),
-       .m4_ack(fml_tmudr_ack),
-       .m4_sel(8'bx),
-       .m4_di(64'bx),
-       .m4_do(fml_tmudr_dr),
-       
-       .s_adr(fml_adr),
-       .s_stb(fml_stb),
-       .s_we(fml_we),
-       .s_ack(fml_ack),
-       .s_sel(fml_sel),
-       .s_di(fml_dr),
-       .s_do(fml_dw)
-);
-
-//---------------------------------------------------------------------------
-// WISHBONE to CSR bridge
-//---------------------------------------------------------------------------
-csrbrg csrbrg(
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .wb_adr_i(csrbrg_adr),
-       .wb_dat_i(csrbrg_dat_w),
-       .wb_dat_o(csrbrg_dat_r),
-       .wb_cyc_i(csrbrg_cyc),
-       .wb_stb_i(csrbrg_stb),
-       .wb_we_i(csrbrg_we),
-       .wb_ack_o(csrbrg_ack),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_do(csr_dw),
-       /* combine all slave->master data lines with an OR */
-       .csr_di(
-                csr_dr_uart
-               |csr_dr_sysctl
-               |csr_dr_hpdmc
-               |csr_dr_vga
-               |csr_dr_ac97
-               |csr_dr_pfpu
-               |csr_dr_tmu
-               |csr_dr_ps2
-               |csr_dr_mouse
-               |csr_dr_ethernet
-               |csr_dr_fmlmeter
-       )
-);
-
-//---------------------------------------------------------------------------
-// WISHBONE to FML bridge
-//---------------------------------------------------------------------------
-wire dcb_stb;
-wire [`SDRAM_DEPTH-1:0] dcb_adr;
-wire [63:0] dcb_dat;
-wire dcb_hit;
-
-fmlbrg #(
-       .fml_depth(`SDRAM_DEPTH)
-) fmlbrg (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .wb_adr_i(brg_adr),
-       .wb_cti_i(brg_cti),
-       .wb_dat_o(brg_dat_r),
-       .wb_dat_i(brg_dat_w),
-       .wb_sel_i(brg_sel),
-       .wb_stb_i(brg_stb),
-       .wb_cyc_i(brg_cyc),
-       .wb_ack_o(brg_ack),
-       .wb_we_i(brg_we),
-       
-       .fml_adr(fml_brg_adr),
-       .fml_stb(fml_brg_stb),
-       .fml_we(fml_brg_we),
-       .fml_ack(fml_brg_ack),
-       .fml_sel(fml_brg_sel),
-       .fml_di(fml_brg_dr),
-       .fml_do(fml_brg_dw),
-
-       .dcb_stb(dcb_stb),
-       .dcb_adr(dcb_adr),
-       .dcb_dat(dcb_dat),
-       .dcb_hit(dcb_hit)
-);
-
-//---------------------------------------------------------------------------
-// Interrupts
-//---------------------------------------------------------------------------
-wire gpio_irq;
-wire timer0_irq;
-wire timer1_irq;
-wire uartrx_irq;
-wire uarttx_irq;
-wire ac97crrequest_irq;
-wire ac97crreply_irq;
-wire ac97dmar_irq;
-wire ac97dmaw_irq;
-wire pfpu_irq;
-wire tmu_irq;
-wire keyboard_irq;
-wire mouse_irq;
-wire ethernetrx_irq;
-wire ethernettx_irq;
-
-wire [31:0] cpu_interrupt;
-assign cpu_interrupt = {17'd0,
-       ethernettx_irq,
-       ethernetrx_irq,
-       mouse_irq,
-       keyboard_irq,
-       tmu_irq,
-       pfpu_irq,
-       ac97dmaw_irq,
-       ac97dmar_irq,
-       ac97crreply_irq,
-       ac97crrequest_irq,
-       uarttx_irq,
-       uartrx_irq,
-       timer1_irq,
-       timer0_irq,
-       gpio_irq
-};
-
-//---------------------------------------------------------------------------
-// LM32 CPU
-//---------------------------------------------------------------------------
-lm32_top cpu(
-       .clk_i(sys_clk),
-       .rst_i(sys_rst),
-       .interrupt(cpu_interrupt),
-
-       .I_ADR_O(cpuibus_adr),
-       .I_DAT_I(cpuibus_dat_r),
-       .I_DAT_O(),
-       .I_SEL_O(),
-       .I_CYC_O(cpuibus_cyc),
-       .I_STB_O(cpuibus_stb),
-       .I_ACK_I(cpuibus_ack),
-       .I_WE_O(),
-       .I_CTI_O(cpuibus_cti),
-       .I_LOCK_O(),
-       .I_BTE_O(),
-       .I_ERR_I(1'b0),
-       .I_RTY_I(1'b0),
-
-       .D_ADR_O(cpudbus_adr),
-       .D_DAT_I(cpudbus_dat_r),
-       .D_DAT_O(cpudbus_dat_w),
-       .D_SEL_O(cpudbus_sel),
-       .D_CYC_O(cpudbus_cyc),
-       .D_STB_O(cpudbus_stb),
-       .D_ACK_I(cpudbus_ack),
-       .D_WE_O (cpudbus_we),
-       .D_CTI_O(cpudbus_cti),
-       .D_LOCK_O(),
-       .D_BTE_O(),
-       .D_ERR_I(1'b0),
-       .D_RTY_I(1'b0)
-);
-
-//---------------------------------------------------------------------------
-// Boot ROM
-//---------------------------------------------------------------------------
-norflash32 #(
-       .adr_width(21)
-) norflash (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .wb_adr_i(norflash_adr),
-       .wb_dat_o(norflash_dat_r),
-       .wb_stb_i(norflash_stb),
-       .wb_cyc_i(norflash_cyc),
-       .wb_ack_o(norflash_ack),
-       
-       .flash_adr(flash_adr[21:1]),
-       .flash_d(flash_d)
-
-);
-
-assign flash_adr[0] = 1'b0;
-assign flash_adr[24:22] = 3'b000;
-
-assign flash_byte_n = 1'b1;
-assign flash_oe_n = 1'b0;
-assign flash_we_n = 1'b1;
-assign flash_ce = 1'b1;
-
-/*
- * Disable the SRAM.
- * Since CE_N is a synchronous input
- * we also clock the SRAM so that
- * we make sure it gets the message.
- */
-assign sram_clk = sys_clk;
-assign sram_ce_n = 1'b1;
-assign sram_zz = 1'b1;
-
-//---------------------------------------------------------------------------
-// UART
-//---------------------------------------------------------------------------
-uart #(
-       .csr_addr(4'h0),
-       .clk_freq(`CLOCK_FREQUENCY),
-       .baud(`BAUD_RATE)
-) uart (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_uart),
-       
-       .rx_irq(uartrx_irq),
-       .tx_irq(uarttx_irq),
-       
-       .uart_rxd(uart_rxd),
-       .uart_txd(uart_txd)
-);
-
-/* LED0 and LED1 are used as TX/RX indicators.
- * Generate long pulses so we have time to see them
- */
-reg [18:0] rxcounter;
-reg rxled;
-always @(posedge sys_clk) begin
-       if(~uart_rxd)
-               rxcounter <= {19{1'b1}};
-       else if(rxcounter != 19'd0)
-               rxcounter <= rxcounter - 19'd1;
-       rxled <= rxcounter != 19'd0;
-end
-
-reg [18:0] txcounter;
-reg txled;
-always @(posedge sys_clk) begin
-       if(~uart_txd)
-               txcounter <= {19{1'b1}};
-       else if(txcounter != 19'd0)
-               txcounter <= txcounter - 20'd1;
-       txled <= txcounter != 19'd0;
-end
-
-assign led[0] = txled;
-assign led[1] = rxled;
-
-//---------------------------------------------------------------------------
-// System Controller
-//---------------------------------------------------------------------------
-wire [13:0] gpio_outputs;
-wire [31:0] capabilities;
-
-sysctl #(
-       .csr_addr(4'h1),
-       .ninputs(13),
-       .noutputs(14),
-       .systemid(32'h58343031) /* X401 */
-) sysctl (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .gpio_irq(gpio_irq),
-       .timer0_irq(timer0_irq),
-       .timer1_irq(timer1_irq),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_sysctl),
-
-       .gpio_inputs({dipsw, btn}),
-       .gpio_outputs(gpio_outputs),
-
-       .capabilities(capabilities),
-       .hard_reset(hard_reset)
-);
-
-gen_capabilities gen_capabilities(
-       .capabilities(capabilities)
-);
-
-/* LED0 and LED1 are used as TX/RX indicators. */
-
-assign led[2] = gpio_outputs[0];
-assign led[3] = gpio_outputs[1];
-assign btnled = gpio_outputs[6:2];
-assign lcd_e = gpio_outputs[7];
-assign lcd_rs = gpio_outputs[8];
-assign lcd_rw = gpio_outputs[9];
-assign lcd_d = gpio_outputs[13:10];
-
-//---------------------------------------------------------------------------
-// SystemACE/USB interface
-//---------------------------------------------------------------------------
-`ifdef ENABLE_ACEUSB
-aceusb aceusb(
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .wb_cyc_i(aceusb_cyc),
-       .wb_stb_i(aceusb_stb),
-       .wb_ack_o(aceusb_ack),
-       .wb_adr_i(aceusb_adr),
-       .wb_dat_i(aceusb_dat_w),
-       .wb_dat_o(aceusb_dat_r),
-       .wb_we_i(aceusb_we),
-       
-       .aceusb_a(aceusb_a),
-       .aceusb_d(aceusb_d),
-       .aceusb_oe_n(aceusb_oe_n),
-       .aceusb_we_n(aceusb_we_n),
-       .ace_clkin(ace_clkin),
-       .ace_mpce_n(ace_mpce_n),
-       .ace_mpirq(ace_mpirq),
-       .usb_cs_n(usb_cs_n),
-       .usb_hpi_reset_n(usb_hpi_reset_n),
-       .usb_hpi_int(usb_hpi_int)
-);
-`else
-assign aceusb_a = 7'd0;
-assign aceusb_d = 16'bz;
-assign aceusb_oe_n = 1'b1;
-assign aceusb_we_n = 1'b1;
-assign ace_mpce_n = 1'b0;
-assign usb_cs_n = 1'b1;
-assign usb_hpi_reset_n = 1'b1;
-assign aceusb_ack = aceusb_cyc & aceusb_stb;
-assign aceusb_dat_r = 32'habadface;
-`endif
-
-//---------------------------------------------------------------------------
-// DDR SDRAM
-//---------------------------------------------------------------------------
-ddram #(
-       .csr_addr(4'h2)
-) ddram (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_hpdmc),
-
-       .fml_adr(fml_adr),
-       .fml_stb(fml_stb),
-       .fml_we(fml_we),
-       .fml_ack(fml_ack),
-       .fml_sel(fml_sel),
-       .fml_di(fml_dw),
-       .fml_do(fml_dr),
-       
-       .sdram_clk_p(sdram_clk_p),
-       .sdram_clk_n(sdram_clk_n),
-       .sdram_clk_fb(sdram_clk_fb),
-       .sdram_cke(sdram_cke),
-       .sdram_cs_n(sdram_cs_n),
-       .sdram_we_n(sdram_we_n),
-       .sdram_cas_n(sdram_cas_n),
-       .sdram_ras_n(sdram_ras_n),
-       .sdram_dqm(sdram_dqm),
-       .sdram_adr(sdram_adr),
-       .sdram_ba(sdram_ba),
-       .sdram_dq(sdram_dq),
-       .sdram_dqs(sdram_dqs)
-);
-
-//---------------------------------------------------------------------------
-// VGA
-//---------------------------------------------------------------------------
-vga #(
-       .csr_addr(4'h3),
-       .fml_depth(`SDRAM_DEPTH)
-) vga (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_vga),
-       
-       .fml_adr(fml_vga_adr),
-       .fml_stb(fml_vga_stb),
-       .fml_ack(fml_vga_ack),
-       .fml_di(fml_vga_dr),
-
-       .dcb_stb(dcb_stb),
-       .dcb_adr(dcb_adr),
-       .dcb_dat(dcb_dat),
-       .dcb_hit(dcb_hit),
-       
-       .vga_psave_n(vga_psave_n),
-       .vga_hsync_n(vga_hsync_n),
-       .vga_vsync_n(vga_vsync_n),
-       .vga_sync_n(vga_sync_n),
-       .vga_blank_n(vga_blank_n),
-       .vga_r(vga_r),
-       .vga_g(vga_g),
-       .vga_b(vga_b),
-       .vga_clkout(vga_clkout)
-);
-
-//---------------------------------------------------------------------------
-// AC97
-//---------------------------------------------------------------------------
-`ifdef ENABLE_AC97
-ac97 #(
-       .csr_addr(4'h4)
-) ac97 (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       .ac97_clk(ac97_clk),
-       .ac97_rst_n(ac97_rst_n),
-       
-       .ac97_sin(ac97_sin),
-       .ac97_sout(ac97_sout),
-       .ac97_sync(ac97_sync),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_ac97),
-       
-       .crrequest_irq(ac97crrequest_irq),
-       .crreply_irq(ac97crreply_irq),
-       .dmar_irq(ac97dmar_irq),
-       .dmaw_irq(ac97dmaw_irq),
-       
-       .wbm_adr_o(ac97bus_adr),
-       .wbm_cti_o(ac97bus_cti),
-       .wbm_we_o(ac97bus_we),
-       .wbm_cyc_o(ac97bus_cyc),
-       .wbm_stb_o(ac97bus_stb),
-       .wbm_ack_i(ac97bus_ack),
-       .wbm_dat_i(ac97bus_dat_r),
-       .wbm_dat_o(ac97bus_dat_w)
-);
-
-`else
-assign csr_dr_ac97 = 32'd0;
-
-assign ac97crrequest_irq = 1'b0;
-assign ac97crreply_irq = 1'b0;
-assign ac97dmar_irq = 1'b0;
-assign ac97dmaw_irq = 1'b0;
-
-assign ac97_sout = 1'b0;
-assign ac97_sync = 1'b0;
-
-assign ac97bus_adr = 32'bx;
-assign ac97bus_cti = 3'bx;
-assign ac97bus_we = 1'bx;
-assign ac97bus_cyc = 1'b0;
-assign ac97bus_stb = 1'b0;
-assign ac97bus_dat_w = 32'bx;
-`endif
-
-//---------------------------------------------------------------------------
-// Programmable FPU
-//---------------------------------------------------------------------------
-`ifdef ENABLE_PFPU
-pfpu #(
-       .csr_addr(4'h5)
-) pfpu (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_pfpu),
-       
-       .irq(pfpu_irq),
-       
-       .wbm_dat_o(pfpubus_dat_w),
-       .wbm_adr_o(pfpubus_adr),
-       .wbm_cyc_o(pfpubus_cyc),
-       .wbm_stb_o(pfpubus_stb),
-       .wbm_ack_i(pfpubus_ack)
-);
-
-`else
-assign csr_dr_pfpu = 32'd0;
-
-assign pfpu_irq = 1'b0;
-
-assign pfpubus_dat_w = 32'hx;
-assign pfpubus_adr = 32'hx;
-assign pfpubus_cyc = 1'b0;
-assign pfpubus_stb = 1'b0;
-`endif
-
-//---------------------------------------------------------------------------
-// Texture Mapping Unit
-//---------------------------------------------------------------------------
-`ifdef ENABLE_TMU
-tmu2 #(
-       .csr_addr(4'h6),
-       .fml_depth(`SDRAM_DEPTH)
-) tmu (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_tmu),
-       
-       .irq(tmu_irq),
-       
-       .wbm_adr_o(tmumbus_adr),
-       .wbm_cti_o(tmumbus_cti),
-       .wbm_cyc_o(tmumbus_cyc),
-       .wbm_stb_o(tmumbus_stb),
-       .wbm_ack_i(tmumbus_ack),
-       .wbm_dat_i(tmumbus_dat_r),
-       
-       .fmlr_adr(fml_tmur_adr),
-       .fmlr_stb(fml_tmur_stb),
-       .fmlr_ack(fml_tmur_ack),
-       .fmlr_di(fml_tmur_dr),
-
-       .fmldr_adr(fml_tmudr_adr),
-       .fmldr_stb(fml_tmudr_stb),
-       .fmldr_ack(fml_tmudr_ack),
-       .fmldr_di(fml_tmudr_dr),
-       
-       .fmlw_adr(fml_tmuw_adr),
-       .fmlw_stb(fml_tmuw_stb),
-       .fmlw_ack(fml_tmuw_ack),
-       .fmlw_sel(fml_tmuw_sel),
-       .fmlw_do(fml_tmuw_dw)
-);
-
-`else
-assign csr_dr_tmu = 32'd0;
-
-assign tmu_irq = 1'b0;
-
-assign tmumbus_adr = 32'hx;
-assign tmumbus_cti = 3'bxxx;
-assign tmumbus_cyc = 1'b0;
-assign tmumbus_stb = 1'b0;
-
-assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
-assign fml_tmur_stb = 1'b0;
-
-assign fml_tmudr_adr = {`SDRAM_DEPTH{1'bx}};
-assign fml_tmudr_stb = 1'b0;
-
-assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
-assign fml_tmuw_stb = 1'b0;
-assign fml_tmuw_sel = 8'bx;
-assign fml_tmuw_dw = 64'bx;
-`endif
-
-//---------------------------------------------------------------------------
-// PS2 Interface
-//---------------------------------------------------------------------------
-`ifdef ENABLE_PS2_KEYBOARD
-ps2 #(
-       .csr_addr(4'h7),
-       .clk_freq(`CLOCK_FREQUENCY)
-) ps2_keyboard (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_ps2),
-
-       .ps2_clk(ps2_clk1),
-       .ps2_data(ps2_data1),
-
-       .irq(keyboard_irq)
-
-);
-`else
-assign csr_dr_ps2 = 32'd0;
-assign keyboard_irq = 1'd0;
-`endif
-`ifdef ENABLE_PS2_MOUSE
-ps2 #(
-       .csr_addr(4'h8),
-       .clk_freq(`CLOCK_FREQUENCY)
-) ps2_mouse (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_mouse),
-
-       .ps2_clk(ps2_clk2),
-       .ps2_data(ps2_data2),
-
-       .irq(mouse_irq)
-
-);
-`else
-assign csr_dr_mouse = 32'd0;
-assign mouse_irq = 1'd0;
-`endif
-
-//---------------------------------------------------------------------------
-// Ethernet
-//---------------------------------------------------------------------------
-`ifdef ENABLE_ETHERNET
-minimac #(
-       .csr_addr(4'h9)
-) ethernet (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_ethernet),
-
-       .wbrx_adr_o(ethernetrxbus_adr),
-       .wbrx_cti_o(ethernetrxbus_cti),
-       .wbrx_cyc_o(ethernetrxbus_cyc),
-       .wbrx_stb_o(ethernetrxbus_stb),
-       .wbrx_ack_i(ethernetrxbus_ack),
-       .wbrx_dat_o(ethernetrxbus_dat_w),
-
-       .wbtx_adr_o(ethernettxbus_adr),
-       .wbtx_cti_o(ethernettxbus_cti),
-       .wbtx_cyc_o(ethernettxbus_cyc),
-       .wbtx_stb_o(ethernettxbus_stb),
-       .wbtx_ack_i(ethernettxbus_ack),
-       .wbtx_dat_i(ethernettxbus_dat_r),
-
-       .irq_rx(ethernetrx_irq),
-       .irq_tx(ethernettx_irq),
-
-       .phy_tx_clk(phy_tx_clk),
-       .phy_tx_data(phy_tx_data),
-       .phy_tx_en(phy_tx_en),
-       .phy_tx_er(phy_tx_er),
-       .phy_rx_clk(phy_rx_clk),
-       .phy_rx_data(phy_rx_data),
-       .phy_dv(phy_dv),
-       .phy_rx_er(phy_rx_er),
-       .phy_col(phy_col),
-       .phy_crs(phy_crs),
-       .phy_mii_clk(phy_mii_clk),
-       .phy_mii_data(phy_mii_data)
-);
-`else
-assign csr_dr_ethernet = 32'd0;
-assign ethernetrxbus_adr = 32'bx;
-assign ethernetrxbus_cti = 3'bx;
-assign ethernetrxbus_cyc = 1'b0;
-assign ethernetrxbus_stb = 1'b0;
-assign ethernetrxbus_dat_w = 32'bx;
-assign ethernettxbus_adr = 32'bx;
-assign ethernettxbus_cti = 3'bx;
-assign ethernettxbus_cyc = 1'b0;
-assign ethernettxbus_stb = 1'b0;
-assign ethernettxbus_dat_r = 32'bx;
-assign ethernetrx_irq = 1'b0;
-assign ethernettx_irq = 1'b0;
-assign phy_tx_data = 4'b0;
-assign phy_tx_en = 1'b0;
-assign phy_tx_er = 1'b0;
-assign phy_mii_clk = 1'b0;
-assign phy_mii_data = 1'bz;
-`endif
-
-//---------------------------------------------------------------------------
-// FastMemoryLink usage and performance meter
-//---------------------------------------------------------------------------
-`ifdef ENABLE_FMLMETER
-fmlmeter #(
-       .csr_addr(4'ha)
-) fmlmeter (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_dw),
-       .csr_do(csr_dr_fmlmeter),
-
-       .fml_stb(fml_stb),
-       .fml_ack(fml_ack)
-);
-`else
-assign csr_dr_fmlmeter = 32'd0;
-`endif
-
-endmodule
diff --git a/boards/xilinx-ml401/rtl/vga.v b/boards/xilinx-ml401/rtl/vga.v
deleted file mode 100644 (file)
index 5bbc857..0000000
+++ /dev/null
@@ -1,98 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`include "setup.v"
-
-module vga #(
-       parameter csr_addr = 4'h0,
-       parameter fml_depth = 26
-) (
-       input sys_clk,
-       input sys_rst,
-       
-       /* Configuration interface */
-       input [13:0] csr_a,
-       input csr_we,
-       input [31:0] csr_di,
-       output [31:0] csr_do,
-       
-       /* Framebuffer FML 4x64 interface */
-       output [fml_depth-1:0] fml_adr,
-       output fml_stb,
-       input fml_ack,
-       input [63:0] fml_di,
-
-       /* Direct Cache Bus */
-       output dcb_stb,
-       output [fml_depth-1:0] dcb_adr,
-       input [63:0] dcb_dat,
-       input dcb_hit,
-       
-       /* VGA pads */
-       output vga_psave_n,
-       output vga_hsync_n,
-       output vga_vsync_n,
-       output vga_sync_n,
-       output vga_blank_n,
-       output [7:0] vga_r,
-       output [7:0] vga_g,
-       output [7:0] vga_b,
-       output vga_clkout
-);
-
-wire vga_clk;
-
-reg [1:0] fcounter;
-always @(posedge sys_clk) fcounter <= fcounter + 2'd1;
-assign vga_clk = fcounter[1];
-
-assign vga_clkout = vga_clk;
-
-vgafb #(
-       .csr_addr(csr_addr),
-       .fml_depth(fml_depth)
-) vgafb (
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-       
-       .csr_a(csr_a),
-       .csr_we(csr_we),
-       .csr_di(csr_di),
-       .csr_do(csr_do),
-       
-       .fml_adr(fml_adr),
-       .fml_stb(fml_stb),
-       .fml_ack(fml_ack),
-       .fml_di(fml_di),
-       
-       .dcb_stb(dcb_stb),
-       .dcb_adr(dcb_adr),
-       .dcb_dat(dcb_dat),
-       .dcb_hit(dcb_hit),
-       
-       .vga_clk(vga_clk),
-       .vga_psave_n(vga_psave_n),
-       .vga_hsync_n(vga_hsync_n),
-       .vga_vsync_n(vga_vsync_n),
-       .vga_sync_n(vga_sync_n),
-       .vga_blank_n(vga_blank_n),
-       .vga_r(vga_r),
-       .vga_g(vga_g),
-       .vga_b(vga_b)
-);
-
-endmodule
diff --git a/boards/xilinx-ml401/sources.mak b/boards/xilinx-ml401/sources.mak
deleted file mode 100644 (file)
index b4b0415..0000000
+++ /dev/null
@@ -1,66 +0,0 @@
-BOARD_SRC=$(wildcard $(BOARD_DIR)/*.v) $(BOARD_DIR)/../../gen_capabilities.v
-
-ASFIFO_SRC=$(wildcard $(CORES_DIR)/asfifo/rtl/*.v)
-CONBUS_SRC=$(wildcard $(CORES_DIR)/conbus/rtl/*.v)
-LM32_SRC=                                              \
-       $(CORES_DIR)/lm32/rtl/lm32_cpu.v                \
-       $(CORES_DIR)/lm32/rtl/lm32_instruction_unit.v   \
-       $(CORES_DIR)/lm32/rtl/lm32_decoder.v            \
-       $(CORES_DIR)/lm32/rtl/lm32_load_store_unit.v    \
-       $(CORES_DIR)/lm32/rtl/lm32_adder.v              \
-       $(CORES_DIR)/lm32/rtl/lm32_addsub.v             \
-       $(CORES_DIR)/lm32/rtl/lm32_logic_op.v           \
-       $(CORES_DIR)/lm32/rtl/lm32_shifter.v            \
-       $(CORES_DIR)/lm32/rtl/lm32_multiplier.v         \
-       $(CORES_DIR)/lm32/rtl/lm32_mc_arithmetic.v      \
-       $(CORES_DIR)/lm32/rtl/lm32_interrupt.v          \
-       $(CORES_DIR)/lm32/rtl/lm32_ram.v                \
-       $(CORES_DIR)/lm32/rtl/lm32_icache.v             \
-       $(CORES_DIR)/lm32/rtl/lm32_dcache.v             \
-       $(CORES_DIR)/lm32/rtl/lm32_top.v
-FMLARB_SRC=$(wildcard $(CORES_DIR)/fmlarb/rtl/*.v)
-FMLBRG_SRC=$(wildcard $(CORES_DIR)/fmlbrg/rtl/*.v)
-CSRBRG_SRC=$(wildcard $(CORES_DIR)/csrbrg/rtl/*.v)
-NORFLASH_SRC=$(wildcard $(CORES_DIR)/norflash32/rtl/*.v)
-UART_SRC=$(wildcard $(CORES_DIR)/uart/rtl/*.v)
-SYSCTL_SRC=$(wildcard $(CORES_DIR)/sysctl/rtl/*.v)
-ACEUSB_SRC=$(wildcard $(CORES_DIR)/aceusb/rtl/*.v)
-HPDMC_SRC=$(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/*.v) $(wildcard $(CORES_DIR)/hpdmc_ddr32/rtl/virtex4/*.v)
-VGAFB_SRC=                                             \
-       $(CORES_DIR)/vgafb/rtl/vgafb_pixelfeed.v        \
-       $(CORES_DIR)/vgafb/rtl/vgafb_ctlif.v            \
-       $(CORES_DIR)/vgafb/rtl/vgafb_fifo64to16.v       \
-       $(CORES_DIR)/vgafb/rtl/vgafb.v
-AC97_SRC=$(wildcard $(CORES_DIR)/ac97/rtl/*.v)
-PFPU_SRC=$(wildcard $(CORES_DIR)/pfpu/rtl/*.v)
-TMU_SRC=                                               \
-       $(CORES_DIR)/tmu2/rtl/tmu2_adrgen.v             \
-       $(CORES_DIR)/tmu2/rtl/tmu2_clamp.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_dpram_sw.v           \
-       $(CORES_DIR)/tmu2/rtl/tmu2_hdiv.v               \
-       $(CORES_DIR)/tmu2/rtl/tmu2_burst.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_pixout.v             \
-       $(CORES_DIR)/tmu2/rtl/tmu2.v                    \
-       $(CORES_DIR)/tmu2/rtl/tmu2_ctlif.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_fetchvertex.v        \
-       $(CORES_DIR)/tmu2/rtl/tmu2_hinterp.v            \
-       $(CORES_DIR)/tmu2/rtl/tmu2_qpram32_ss.v         \
-       $(CORES_DIR)/tmu2/rtl/tmu2_vdivops.v            \
-       $(CORES_DIR)/tmu2/rtl/tmu2_decay.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_geninterp18.v        \
-       $(CORES_DIR)/tmu2/rtl/tmu2_mask.v               \
-       $(CORES_DIR)/tmu2/rtl/tmu2_qpram.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_vdiv.v               \
-       $(CORES_DIR)/tmu2/rtl/tmu2_divider17.v          \
-       $(CORES_DIR)/tmu2/rtl/tmu2_hdivops.v            \
-       $(CORES_DIR)/tmu2/rtl/tmu2_texcache.v           \
-       $(CORES_DIR)/tmu2/rtl/tmu2_vinterp.v            \
-       $(CORES_DIR)/tmu2/rtl/tmu2_blend.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_mult2_virtex4.v      \
-       $(CORES_DIR)/tmu2/rtl/tmu2_fdest.v              \
-       $(CORES_DIR)/tmu2/rtl/tmu2_alpha.v
-PS2_SRC=$(wildcard $(CORES_DIR)/ps2/rtl/*.v)
-ETHERNET_SRC=$(wildcard $(CORES_DIR)/minimac/rtl/*.v)
-FMLMETER_SRC=$(wildcard $(CORES_DIR)/fmlmeter/rtl/*.v)
-
-CORES_SRC=$(ASFIFO_SRC) $(CONBUS_SRC) $(LM32_SRC) $(FMLARB_SRC) $(FMLBRG_SRC) $(CSRBRG_SRC) $(NORFLASH_SRC) $(UART_SRC) $(SYSCTL_SRC) $(ACEUSB_SRC) $(HPDMC_SRC) $(VGAFB_SRC) $(AC97_SRC) $(PFPU_SRC) $(TMU_SRC) $(PS2_SRC) $(ETHERNET_SRC) $(FMLMETER_SRC)
diff --git a/boards/xilinx-ml401/synthesis/Makefile.precision b/boards/xilinx-ml401/synthesis/Makefile.precision
deleted file mode 100644 (file)
index 7b3005a..0000000
+++ /dev/null
@@ -1,29 +0,0 @@
-BOARD_DIR=../rtl
-CORES_DIR=../../../cores
-
-include ../sources.mak
-SRC=$(BOARD_SRC) $(CORES_SRC)
-
-all: build/system.bit
-
-build/system.ucf: common.ucf precision.ucf
-       cat common.ucf precision.ucf > build/system.ucf
-
-build/loadsources.tcl: $(SRC)
-       rm -f build/loadsources.tcl
-       for i in `echo $^`; do \
-           echo "add_input_file ../$$i" >> build/loadsources.tcl; \
-       done
-
-build/milkymist_impl/system.ucf: build/milkymist_impl/system.edf
-
-build/milkymist_impl/system.edf: build/loadsources.tcl build/system.ucf
-       rm -f build/milkymist.psp
-       rm -rf build/milkymist_impl
-       rm -rf build/milkymist_temp*
-       cd build && precision -shell -file ../precision.tcl
-
-build/system.ngd: build/milkymist_impl/system.edf
-       cd build && ngdbuild -uc milkymist_impl/system.ucf milkymist_impl/system.edf
-
-include common.mak
diff --git a/boards/xilinx-ml401/synthesis/Makefile.synplify b/boards/xilinx-ml401/synthesis/Makefile.synplify
deleted file mode 100644 (file)
index 78672fb..0000000
+++ /dev/null
@@ -1,34 +0,0 @@
-BOARD_DIR=../rtl
-CORES_DIR=../../../cores
-
-include ../sources.mak
-SRC=$(BOARD_SRC) $(CORES_SRC)
-
-all: build/system.bit
-
-build/system.ucf: common.ucf synplify.ucf
-       cat common.ucf synplify.ucf > build/system.ucf
-
-build/loadsources.tcl: $(SRC)
-       rm -f build/loadsources.tcl
-       for i in `echo $^`; do \
-           echo "add_file -verilog -lib work \"../$$i\"" >> build/loadsources.tcl; \
-       done
-
-build/system.sdc: build/system.ucf
-       cd build && ucf2sdc -osdc system.sdc -iucf system.ucf
-
-build/synplicity.ucf: build/system.edf
-
-# YES ! Synplify is dirty enough to put all its bloated crapware in the script
-# directory rather than in the current directory. Work around this.
-build/synplify.prj: synplify.prj
-       cp synplify.prj build/synplify.prj
-
-build/system.edf: build/loadsources.tcl build/synplify.prj build/system.sdc
-       cd build && synplify_pro -batch synplify.prj
-
-build/system.ngd: build/system.edf build/synplicity.ucf
-       cd build && ngdbuild -uc synplicity.ucf system.edf
-
-include common.mak
diff --git a/boards/xilinx-ml401/synthesis/Makefile.xst b/boards/xilinx-ml401/synthesis/Makefile.xst
deleted file mode 100644 (file)
index 460182c..0000000
+++ /dev/null
@@ -1,25 +0,0 @@
-BOARD_DIR=../rtl
-CORES_DIR=../../../cores
-
-include ../sources.mak
-SRC=$(BOARD_SRC) $(CORES_SRC)
-
-all: build/system.bit
-
-build/system.ucf: common.ucf xst.ucf
-       cat common.ucf xst.ucf > build/system.ucf
-
-build/system.prj: $(SRC)
-       rm -f build/system.prj
-       for i in `echo $^`; do \
-           echo "verilog work ../$$i" >> build/system.prj; \
-       done
-
-build/system.ngc: build/system.prj
-       cd build && xst -ifn ../system.xst
-
-build/system.ngd: build/system.ngc build/system.ucf
-       cd build && ngdbuild -uc system.ucf system.ngc
-
-include common.mak
-
diff --git a/boards/xilinx-ml401/synthesis/build/.keep_me b/boards/xilinx-ml401/synthesis/build/.keep_me
deleted file mode 100644 (file)
index e69de29..0000000
diff --git a/boards/xilinx-ml401/synthesis/common.mak b/boards/xilinx-ml401/synthesis/common.mak
deleted file mode 100644 (file)
index 8c5797c..0000000
+++ /dev/null
@@ -1,35 +0,0 @@
-prom: build/system.mcs
-
-timing: build/system-routed.twr
-
-usage: build/system-routed.xdl
-       ../../../tools/xdlanalyze.pl build/system-routed.xdl 0
-
-load: build/system.bit
-       cd build && impact -batch ../load.cmd
-
-flash: build/system.mcs
-       cd build && impact -batch ../flash.cmd
-
-build/system.ncd: build/system.ngd
-       cd build && map system.ngd
-
-build/system-routed.ncd: build/system.ncd
-       cd build && par -ol high -w system.ncd system-routed.ncd
-
-build/system.bit: build/system-routed.ncd
-       cd build && bitgen -w system-routed.ncd system.bit
-
-build/system.mcs: build/system.bit
-       cd build && promgen -w -u 0 system
-
-build/system-routed.xdl: build/system-routed.ncd
-       cd build && xdl -ncd2xdl system-routed.ncd system-routed.xdl
-
-build/system-routed.twr: build/system-routed.ncd
-       cd build && trce -v 10 system-routed.ncd system.pcf
-
-clean:
-       rm -rf build/*
-
-.PHONY: prom timing usage load clean
diff --git a/boards/xilinx-ml401/synthesis/common.ucf b/boards/xilinx-ml401/synthesis/common.ucf
deleted file mode 100644 (file)
index 0fc9914..0000000
+++ /dev/null
@@ -1,390 +0,0 @@
-# ==== Clock input ====
-NET "clkin" LOC = AE14 | IOSTANDARD = LVCMOS33;
-
-NET "clkin" TNM_NET = "clkin";
-TIMESPEC "TSclkin" = PERIOD "clkin" 10 ns HIGH 50% INPUT_JITTER 100 ps;
-
-# ==== Reset button ====
-NET "resetin" LOC = D6 | IOSTANDARD = LVCMOS25;
-
-# ==== Linear Flash ====
-NET "flash_adr(0)" LOC = T20;
-NET "flash_adr(1)" LOC = Y1;
-NET "flash_adr(2)" LOC = Y2;
-NET "flash_adr(3)" LOC = AA1;
-NET "flash_adr(4)" LOC = AB1;
-NET "flash_adr(5)" LOC = AB2;
-NET "flash_adr(6)" LOC = AC1;
-NET "flash_adr(7)" LOC = AC2;
-NET "flash_adr(8)" LOC = AD1;
-NET "flash_adr(9)" LOC = AD2;
-NET "flash_adr(10)" LOC = AE3;
-NET "flash_adr(11)" LOC = AF3;
-NET "flash_adr(12)" LOC = W3;
-NET "flash_adr(13)" LOC = W6;
-NET "flash_adr(14)" LOC = W5;
-NET "flash_adr(15)" LOC = AA3;
-NET "flash_adr(16)" LOC = AA4;
-NET "flash_adr(17)" LOC = AB3;
-NET "flash_adr(18)" LOC = AB4;
-NET "flash_adr(19)" LOC = AC4;
-NET "flash_adr(20)" LOC = AB5;
-NET "flash_adr(21)" LOC = AC5;
-NET "flash_adr(22)" LOC = T19;
-NET "flash_adr(23)" LOC = U20;
-NET "flash_adr(24)" LOC = T21;
-
-NET "flash_adr(*)" IOSTANDARD = LVDCI_33;
-NET "flash_adr(*)" SLEW = FAST;
-NET "flash_adr(*)" DRIVE = 8;
-
-NET "flash_d(0)" LOC = AD13;
-NET "flash_d(1)" LOC = AC13;
-NET "flash_d(2)" LOC = AC15;
-NET "flash_d(3)" LOC = AC16;
-NET "flash_d(4)" LOC = AA11;
-NET "flash_d(5)" LOC = AA12;
-NET "flash_d(6)" LOC = AD14;
-NET "flash_d(7)" LOC = AC14;
-NET "flash_d(8)" LOC = AA13;
-NET "flash_d(9)" LOC = AB13;
-NET "flash_d(10)" LOC = AA15;
-NET "flash_d(11)" LOC = AA16;
-NET "flash_d(12)" LOC = AC11;
-NET "flash_d(13)" LOC = AC12;
-NET "flash_d(14)" LOC = AB14;
-NET "flash_d(15)" LOC = AA14;
-NET "flash_d(16)" LOC = D12;
-NET "flash_d(17)" LOC = E13;
-NET "flash_d(18)" LOC = C16;
-NET "flash_d(19)" LOC = D16;
-NET "flash_d(20)" LOC = D11;
-NET "flash_d(21)" LOC = C11;
-NET "flash_d(22)" LOC = E14;
-NET "flash_d(23)" LOC = D15;
-NET "flash_d(24)" LOC = D13;
-NET "flash_d(25)" LOC = D14;
-NET "flash_d(26)" LOC = F15;
-NET "flash_d(27)" LOC = F16;
-NET "flash_d(28)" LOC = F11;
-NET "flash_d(29)" LOC = F12;
-NET "flash_d(30)" LOC = F13;
-NET "flash_d(31)" LOC = F14;
-
-NET "flash_d(*)" IOSTANDARD = LVCMOS33;
-NET "flash_d(*)" PULLDOWN;
-
-NET "flash_byte_n" LOC = N22;
-NET "flash_byte_n" IOSTANDARD = LVDCI_33;
-NET "flash_byte_n" SLEW = FAST;
-NET "flash_byte_n" DRIVE = 8;
-
-NET "flash_oe_n" LOC = AC6;
-NET "flash_oe_n" IOSTANDARD = LVDCI_33;
-NET "flash_oe_n" SLEW = FAST;
-NET "flash_oe_n" DRIVE = 8;
-
-NET "flash_we_n" LOC = AB6;
-NET "flash_we_n" IOSTANDARD = LVDCI_33;
-NET "flash_we_n" SLEW = FAST;
-NET "flash_we_n" DRIVE = 8;
-
-NET "flash_ce" LOC = W7;
-NET "flash_ce" IOSTANDARD = LVDCI_33;
-NET "flash_ce" SLEW = FAST;
-NET "flash_ce" DRIVE = 8;
-
-NET "flash_ac97_reset_n" LOC = AD10;
-NET "flash_ac97_reset_n" IOSTANDARD = LVCMOS33;
-
-# We do not use the SRAM, but we need
-# to get the clock and select signals
-# to disable it in a non-Murphy-prone way.
-NET "sram_clk" LOC = AF7;
-NET "sram_clk" IOSTANDARD = LVCMOS33;
-NET "sram_clk" DRIVE = 16;
-NET "sram_clk" SLEW = FAST;
-
-NET "sram_ce_n" LOC = V7;
-NET "sram_ce_n" IOSTANDARD = LVDCI_33;
-NET "sram_ce_n" SLEW = FAST;
-NET "sram_ce_n" DRIVE = 8;
-
-NET "sram_zz" LOC = V25;
-NET "sram_zz" IOSTANDARD = LVDCI_33;
-NET "sram_zz" SLEW = FAST;
-NET "sram_zz" DRIVE = 8;
-
-# ==== UART ====
-NET "uart_rxd" LOC = W2 | IOSTANDARD = LVCMOS33;
-NET "uart_txd" LOC = W1 | IOSTANDARD = LVCMOS33;
-
-# ==== Push buttons ====
-NET "btn(0)" LOC = E7 | IOSTANDARD = LVCMOS25;  # N
-NET "btn(1)" LOC = E9  | IOSTANDARD = LVCMOS25; # W
-NET "btn(2)" LOC = A6 | IOSTANDARD = LVCMOS25;  # S
-NET "btn(3)" LOC = F10 | IOSTANDARD = LVCMOS25; # E
-NET "btn(4)" LOC = B6 | IOSTANDARD = LVCMOS25;  # C
-
-# ==== Push button LEDs ====
-NET "btnled(0)" LOC = E2 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;  # N
-NET "btnled(1)" LOC = F9 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;  # W
-NET "btnled(2)" LOC = A5 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;  # S
-NET "btnled(3)" LOC = E10 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8; # E
-NET "btnled(4)" LOC = C6 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;  # C
-
-# ==== LEDs ====
-NET "led(0)" LOC = G5 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;
-NET "led(1)" LOC = G6 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;
-NET "led(2)" LOC = A11 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;
-NET "led(3)" LOC = A12 | IOSTANDARD = LVCMOS25 | SLEW = SLOW | DRIVE = 8;
-
-# ==== DIP switches ====
-NET "dipsw(0)" LOC = R20 | IOSTANDARD = LVCMOS33;
-NET "dipsw(1)" LOC = R19 | IOSTANDARD = LVCMOS33;
-NET "dipsw(2)" LOC = T26 | IOSTANDARD = LVCMOS33;
-NET "dipsw(3)" LOC = U26 | IOSTANDARD = LVCMOS33;
-NET "dipsw(4)" LOC = U23 | IOSTANDARD = LVCMOS33;
-NET "dipsw(5)" LOC = V23 | IOSTANDARD = LVCMOS33;
-NET "dipsw(6)" LOC = U25 | IOSTANDARD = LVCMOS33;
-NET "dipsw(7)" LOC = U24 | IOSTANDARD = LVCMOS33;
-
-# ==== Character LCD ====
-NET "lcd_e" LOC = AE13 | IOSTANDARD = LVCMOS33;
-NET "lcd_rs" LOC = AC17 | IOSTANDARD = LVCMOS33;
-NET "lcd_rw" LOC = AB17 | IOSTANDARD = LVCMOS33;
-NET "lcd_d(0)" LOC = AB10 | IOSTANDARD = LVCMOS33; # DB4
-NET "lcd_d(1)" LOC = AC10 | IOSTANDARD = LVCMOS33; # DB5
-NET "lcd_d(2)" LOC = AE12 | IOSTANDARD = LVCMOS33; # DB6
-NET "lcd_d(3)" LOC = AF12 | IOSTANDARD = LVCMOS33; # DB7
-
-# ==== DDR SDRAM ====
-NET "sdram_adr(0)" LOC = C26;
-NET "sdram_adr(1)" LOC = E17;
-NET "sdram_adr(2)" LOC = D18;
-NET "sdram_adr(3)" LOC = C19;
-NET "sdram_adr(4)" LOC = F17;
-NET "sdram_adr(5)" LOC = B18;
-NET "sdram_adr(6)" LOC = B20;
-NET "sdram_adr(7)" LOC = C20;
-NET "sdram_adr(8)" LOC = D20;
-NET "sdram_adr(9)" LOC = C21;
-NET "sdram_adr(10)" LOC = A18;
-NET "sdram_adr(11)" LOC = B21;
-NET "sdram_adr(12)" LOC = A24;
-NET "sdram_ba(0)" LOC = B12;
-NET "sdram_ba(1)" LOC = A16;
-NET "sdram_cas_n" LOC = F23;
-NET "sdram_cke" LOC = G22;
-NET "sdram_cs_n" LOC = G21;
-NET "sdram_ras_n" LOC = F24;
-NET "sdram_we_n" LOC = A23;
-
-NET "sdram_clk_p" LOC = A10;
-NET "sdram_clk_fb" LOC = B13;
-NET "sdram_clk_n" LOC = B10;
-
-NET "sdram_dqm(0)" LOC = G19;
-NET "sdram_dqm(1)" LOC = G24;
-NET "sdram_dqm(2)" LOC = G20;
-NET "sdram_dqm(3)" LOC = C22;
-
-NET "sdram_dqs(0)" LOC = D25;
-NET "sdram_dqs(1)" LOC = G18;
-NET "sdram_dqs(2)" LOC = G17;
-NET "sdram_dqs(3)" LOC = D26;
-
-NET "sdram_dq(0)" LOC = H20;
-NET "sdram_dq(1)" LOC = E23;
-NET "sdram_dq(2)" LOC = H26;
-NET "sdram_dq(3)" LOC = H22;
-NET "sdram_dq(4)" LOC = E25;
-NET "sdram_dq(5)" LOC = E26;
-NET "sdram_dq(6)" LOC = F26;
-NET "sdram_dq(7)" LOC = E24;
-NET "sdram_dq(8)" LOC = E20;
-NET "sdram_dq(9)" LOC = A22;
-NET "sdram_dq(10)" LOC = C23;
-NET "sdram_dq(11)" LOC = C24;
-NET "sdram_dq(12)" LOC = A20;
-NET "sdram_dq(13)" LOC = A21;
-NET "sdram_dq(14)" LOC = D24;
-NET "sdram_dq(15)" LOC = E18;
-NET "sdram_dq(16)" LOC = F18;
-NET "sdram_dq(17)" LOC = A19;
-NET "sdram_dq(18)" LOC = F19;
-NET "sdram_dq(19)" LOC = B23;
-NET "sdram_dq(20)" LOC = E21;
-NET "sdram_dq(21)" LOC = D22;
-NET "sdram_dq(22)" LOC = D23;
-NET "sdram_dq(23)" LOC = B24;
-NET "sdram_dq(24)" LOC = E22;
-NET "sdram_dq(25)" LOC = F20;
-NET "sdram_dq(26)" LOC = H23;
-NET "sdram_dq(27)" LOC = G25;
-NET "sdram_dq(28)" LOC = G26;
-NET "sdram_dq(29)" LOC = H25;
-NET "sdram_dq(30)" LOC = H24;
-NET "sdram_dq(31)" LOC = H21;
-
-NET "sdram_adr(*)" IOSTANDARD = SSTL2_I;
-NET "sdram_ba(*)" IOSTANDARD = SSTL2_I;
-NET "sdram_cas_n" IOSTANDARD = SSTL2_I;
-NET "sdram_cke" IOSTANDARD = SSTL2_I;
-NET "sdram_clk_p" IOSTANDARD = SSTL2_I;
-NET "sdram_clk_fb" IOSTANDARD = LVCMOS25;
-NET "sdram_clk_n" IOSTANDARD = SSTL2_I;
-NET "sdram_cs_n" IOSTANDARD = SSTL2_I;
-NET "sdram_ras_n" IOSTANDARD = SSTL2_I;
-NET "sdram_we_n" IOSTANDARD = SSTL2_I;
-
-NET "sdram_dqs(*)" IOSTANDARD = SSTL2_II;
-NET "sdram_dqm(*)" IOSTANDARD = SSTL2_II;
-NET "sdram_dq(*)" IOSTANDARD = SSTL2_II;
-
-# ==== VGA output ====
-NET "vga_r(0)" LOC = N23 | IOSTANDARD = LVCMOS33; # yes, 3.3V for the 3 LSBs
-NET "vga_r(1)" LOC = N24 | IOSTANDARD = LVCMOS33;
-NET "vga_r(2)" LOC = N25 | IOSTANDARD = LVCMOS33;
-NET "vga_r(3)" LOC = C2 | IOSTANDARD = LVCMOS25; # and 2.5V for the rest
-NET "vga_r(4)" LOC = G7 | IOSTANDARD = LVCMOS25;
-NET "vga_r(5)" LOC = F7 | IOSTANDARD = LVCMOS25;
-NET "vga_r(6)" LOC = E5 | IOSTANDARD = LVCMOS25;
-NET "vga_r(7)" LOC = E6 | IOSTANDARD = LVCMOS25;
-
-NET "vga_r(*)" SLEW = FAST | DRIVE = 8;
-
-NET "vga_g(0)" LOC = M22 | IOSTANDARD = LVCMOS33;
-NET "vga_g(1)" LOC = M23 | IOSTANDARD = LVCMOS33;
-NET "vga_g(2)" LOC = M20 | IOSTANDARD = LVCMOS33;
-NET "vga_g(3)" LOC = E4 | IOSTANDARD = LVCMOS25;
-NET "vga_g(4)" LOC = D3 | IOSTANDARD = LVCMOS25;
-NET "vga_g(5)" LOC = H7 | IOSTANDARD = LVCMOS25;
-NET "vga_g(6)" LOC = H8 | IOSTANDARD = LVCMOS25;
-NET "vga_g(7)" LOC = C1 | IOSTANDARD = LVCMOS25;
-
-NET "vga_g(*)" SLEW = FAST | DRIVE = 8;
-
-NET "vga_b(0)" LOC = M21 | IOSTANDARD = LVCMOS33;
-NET "vga_b(1)" LOC = M26 | IOSTANDARD = LVCMOS33;
-NET "vga_b(2)" LOC = L26 | IOSTANDARD = LVCMOS33;
-NET "vga_b(3)" LOC = C5 | IOSTANDARD = LVCMOS25;
-NET "vga_b(4)" LOC = C7 | IOSTANDARD = LVCMOS25;
-NET "vga_b(5)" LOC = B7 | IOSTANDARD = LVCMOS25;
-NET "vga_b(6)" LOC = G8 | IOSTANDARD = LVCMOS25;
-NET "vga_b(7)" LOC = F8 | IOSTANDARD = LVCMOS25;
-
-NET "vga_b(*)" SLEW = FAST | DRIVE = 8;
-
-NET "vga_vsync_n" LOC = A8 | IOSTANDARD = LVCMOS25 | SLEW = FAST | DRIVE = 8;
-NET "vga_hsync_n" LOC = C10 | IOSTANDARD = LVCMOS25 | SLEW = FAST | DRIVE = 8;
-NET "vga_clkout" LOC = AF8 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
-NET "vga_psave_n" LOC = M25 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
-NET "vga_blank_n" LOC = M24 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
-NET "vga_sync_n" LOC = L23 | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
-
-# ==== SystemACE/USB ====
-
-# Shared signals
-NET "aceusb_a(0)" LOC = U22;
-NET "aceusb_a(1)" LOC = Y10;
-NET "aceusb_a(2)" LOC = AA10;
-NET "aceusb_a(3)" LOC = AC7;
-NET "aceusb_a(4)" LOC = Y7;
-NET "aceusb_a(5)" LOC = AA9;
-NET "aceusb_a(6)" LOC = Y9;
-NET "aceusb_a(*)" IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
-NET "aceusb_d(0)" LOC = AB7;
-NET "aceusb_d(1)" LOC = AC9;
-NET "aceusb_d(2)" LOC = AB9;
-NET "aceusb_d(3)" LOC = AE6;
-NET "aceusb_d(4)" LOC = AD6;
-NET "aceusb_d(5)" LOC = AF9;
-NET "aceusb_d(6)" LOC = AE9;
-NET "aceusb_d(7)" LOC = AD8;
-NET "aceusb_d(8)" LOC = AC8;
-NET "aceusb_d(9)" LOC = AF4;
-NET "aceusb_d(10)" LOC = AE4;
-NET "aceusb_d(11)" LOC = AD3;
-NET "aceusb_d(12)" LOC = AC3;
-NET "aceusb_d(13)" LOC = AF6;
-NET "aceusb_d(14)" LOC = AF5;
-NET "aceusb_d(15)" LOC = AA7;
-NET "aceusb_d(*)" IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4 | PULLDOWN;
-NET "aceusb_oe_n" LOC = AA8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
-NET "aceusb_we_n" LOC = Y8 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
-
-# SystemACE signals
-NET "ace_clkin" LOC = AF11;
-NET "ace_clkin" IOSTANDARD = LVCMOS33;
-NET "ace_clkin" TNM_NET = "ace_clkin";
-# leave 1ns margin (as in the ML401 UCF from Xilinx)
-TIMESPEC "TSace" = PERIOD "ace_clkin" 29 ns HIGH 50%;
-
-NET "ace_mpce_n" LOC = AD5 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
-NET "ace_mpirq" LOC = AD4 | IOSTANDARD = LVCMOS33 | PULLDOWN;
-
-# USB signals
-NET "usb_cs_n" LOC = AF10 | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 4;
-NET "usb_hpi_reset_n" LOC = A7 | IOSTANDARD = LVCMOS25;
-NET "usb_hpi_int" LOC = V5 | IOSTANDARD = LVCMOS33 | PULLDOWN;
-
-# ==== AC97 ====
-NET "ac97_clk" LOC = AE10 | IOSTANDARD = LVCMOS33;
-NET "ac97_sin" LOC = AD16 | IOSTANDARD = LVCMOS33; # codec to FPGA
-NET "ac97_sout" LOC = C8 | IOSTANDARD = LVCMOS25;  # FPGA to codec
-NET "ac97_sync" LOC = D9 | IOSTANDARD = LVCMOS25;
-# reset is shared with Flash (see above)
-
-NET "ac97_clk" TNM_NET = "clkac97";
-TIMESPEC "TSclkac97" = PERIOD "clkac97" 80 HIGH 50%;
-
-# ==== PS/2 ====
-# "keyboard" connector
-NET "ps2_clk1"  LOC = D2 | IOSTANDARD = LVCMOS25;
-NET "ps2_data1" LOC = G9 | IOSTANDARD = LVCMOS25;
-# "mouse" connector
-NET "ps2_clk2"  LOC = B14 | IOSTANDARD = LVCMOS25;
-NET "ps2_data2" LOC = C14 | IOSTANDARD = LVCMOS25;
-
-# ==== Ethernet ====
-NET "phy_col" LOC = E3;
-NET "phy_crs" LOC = D5;
-NET "phy_dv" LOC = A9;
-NET "phy_rx_clk" LOC = B15;
-NET "phy_rx_data<3>" LOC = C4;
-NET "phy_rx_data<2>" LOC = D4;
-NET "phy_rx_data<1>" LOC = E1;
-NET "phy_rx_data<0>" LOC = F1;
-
-NET "phy_rx_er" LOC = B9;
-NET "phy_tx_clk" LOC = C15;
-NET "phy_mii_clk" LOC = D1;
-NET "phy_rst_n" LOC = D10;
-NET "phy_tx_data<3>" LOC = G1;
-NET "phy_tx_data<2>" LOC = H3;
-NET "phy_tx_data<1>" LOC = H2;
-NET "phy_tx_data<0>" LOC = H1;
-NET "phy_tx_en" LOC = F4;
-NET "phy_tx_er" LOC = F3;
-NET "phy_mii_data" LOC = G4;
-
-# Timing
-NET "phy_rx_clk" TNM_NET = "RXCLK_GRP";
-NET "phy_tx_clk" TNM_NET = "TXCLK_GRP";
-TIMESPEC "TSTXOUT" = FROM "TXCLK_GRP" TO "PADS" 10 ns;
-TIMESPEC "TSRXIN" = FROM "PADS" TO "RXCLK_GRP" 6 ns;
-
-NET "phy_tx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" MAXSKEW= 1.0 ns;
-NET "phy_rx_clk" PERIOD = 40 ns HIGH 14 ns;
-NET "phy_tx_clk" PERIOD = 40 ns HIGH 14 ns;
-
-NET "phy_rx_data<3>" IOBDELAY=NONE;
-NET "phy_rx_data<2>" IOBDELAY=NONE;
-NET "phy_rx_data<1>" IOBDELAY=NONE;
-NET "phy_rx_data<0>" IOBDELAY=NONE;
-NET "phy_dv" IOBDELAY=NONE;
-NET "phy_rx_er" IOBDELAY=NONE;
-NET "phy_crs" IOBDELAY=NONE;
-NET "phy_col" IOBDELAY=NONE;
diff --git a/boards/xilinx-ml401/synthesis/flash.cmd b/boards/xilinx-ml401/synthesis/flash.cmd
deleted file mode 100644 (file)
index ad0e8b8..0000000
+++ /dev/null
@@ -1,7 +0,0 @@
-setMode -bscan
-setCable -p auto
-identify
-assignfile -p 2 -file system.mcs
-erase -p 2
-program -p 2
-quit
diff --git a/boards/xilinx-ml401/synthesis/ioffs.sdc b/boards/xilinx-ml401/synthesis/ioffs.sdc
deleted file mode 100644 (file)
index 9fd9ced..0000000
+++ /dev/null
@@ -1 +0,0 @@
-define_global_attribute syn_useioff 1
diff --git a/boards/xilinx-ml401/synthesis/load.cmd b/boards/xilinx-ml401/synthesis/load.cmd
deleted file mode 100644 (file)
index 7c42f2b..0000000
+++ /dev/null
@@ -1,6 +0,0 @@
-setMode -bscan
-setCable -p auto
-identify
-assignfile -p 3 -file system.bit
-program -p 3
-quit
diff --git a/boards/xilinx-ml401/synthesis/precision.tcl b/boards/xilinx-ml401/synthesis/precision.tcl
deleted file mode 100644 (file)
index 90b18f9..0000000
+++ /dev/null
@@ -1,20 +0,0 @@
-new_project -name "milkymist" -folder "." -createimpl_name "milkymist_impl"
-
-setup_design -manufacturer "Xilinx" -family "VIRTEX-4" -part "4VLX25FF668" -speed "10"
-setup_design -retiming
-setup_design -max_fanout=10000
-setup_design -design "system"
-setup_design -basename "system"
-
-setup_design -compile_for_area=false
-setup_design -compile_for_timing=true
-
-source "loadsources.tcl"
-add_input_file "system.ucf" -exclude="false"
-add_input_file "../ioffs.sdc"
-
-compile
-synthesize
-
-save_impl
-close_project
diff --git a/boards/xilinx-ml401/synthesis/precision.ucf b/boards/xilinx-ml401/synthesis/precision.ucf
deleted file mode 100644 (file)
index c2bf17b..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-# LOC the DCMs related to SDRAM and the input BUFG
-# to prevent tools from randomly screwing up
-# the DDR timings when the design is changed.
-INST "clkbuf" LOC = BUFGCTRL_X0Y9;
-INST "ddram_clkgen_sdram" LOC = DCM_ADV_X0Y3;
-INST "ddram_clkgen_dqs" LOC = DCM_ADV_X0Y4;
-
-# 25MHz pixel clock only for now
-NET "vga_clk" TNM_NET = "clkvga";
-TIMESPEC "TSclkvga" = PERIOD "clkvga" 40 HIGH 50%;
-
-CONFIG STEPPING="ES";
diff --git a/boards/xilinx-ml401/synthesis/synplify.prj b/boards/xilinx-ml401/synthesis/synplify.prj
deleted file mode 100644 (file)
index 5082723..0000000
+++ /dev/null
@@ -1,30 +0,0 @@
-set_option -vlog_std v2001
-
-source "loadsources.tcl"
-add_file "system.sdc"
-add_file "../ioffs.sdc"
-
-set_option -technology VIRTEX4
-set_option -part XC4VLX25
-set_option -package FF668
-set_option -speed_grade -10
-
-set_option -top_module system
-
-set_option -default_enum_encoding onehot
-set_option -symbolic_fsm_compiler 0
-set_option -resource_sharing 0
-
-set_option -fanout_limit 10000
-set_option -maxfan_hard 0
-set_option -retiming 1
-set_option -pipe 0
-set_option -disable_io_insertion 0
-
-set_option -include_path "../../../../cores/pfpu/rtl/;../../rtl/"
-
-set_option -write_verilog false
-
-set_option -write_apr_constraint true
-
-project -result_file "system.edf"
diff --git a/boards/xilinx-ml401/synthesis/synplify.ucf b/boards/xilinx-ml401/synthesis/synplify.ucf
deleted file mode 100644 (file)
index c0be01a..0000000
+++ /dev/null
@@ -1,11 +0,0 @@
-# LOC the DCMs related to SDRAM and the input BUFG
-# to prevent tools from randomly screwing up
-# the DDR timings when the design is changed.
-INST "clkbuf" LOC = BUFGCTRL_X0Y9;
-INST "ddram/clkgen_sdram" LOC = DCM_ADV_X0Y3;
-INST "ddram/clkgen_dqs" LOC = DCM_ADV_X0Y4;
-
-# 25MHz pixel clock only for now
-NET "vga/fcounter(1)" TNM_NET = "clkvga";
-TIMESPEC "TSclkvga" = PERIOD "clkvga" 40 HIGH 50%;
-
diff --git a/boards/xilinx-ml401/synthesis/system.xst b/boards/xilinx-ml401/synthesis/system.xst
deleted file mode 100644 (file)
index f44d872..0000000
+++ /dev/null
@@ -1,9 +0,0 @@
-run
--ifn system.prj
--top system
--ifmt MIXED
--opt_mode SPEED
--opt_level 2
--ofn system.ngc
--p xc4vlx25-ff668-10
--register_balancing yes
diff --git a/boards/xilinx-ml401/synthesis/xst.ucf b/boards/xilinx-ml401/synthesis/xst.ucf
deleted file mode 100644 (file)
index 5b132af..0000000
+++ /dev/null
@@ -1,12 +0,0 @@
-# LOC the DCMs related to SDRAM and the input BUFG
-# to prevent tools from randomly screwing up
-# the DDR timings when the design is changed.
-INST "clkbuf" LOC = BUFGCTRL_X0Y9;
-INST "ddram/clkgen_sdram" LOC = DCM_ADV_X0Y3;
-INST "ddram/clkgen_dqs" LOC = DCM_ADV_X0Y4;
-
-# 25MHz pixel clock only for now
-NET "vga/fcounter(1)" TNM_NET = "clkvga";
-TIMESPEC "TSclkvga" = PERIOD "clkvga" 40 HIGH 50%;
-
-CONFIG STEPPING="ES";
diff --git a/boards/xilinx-ml401/test/Makefile b/boards/xilinx-ml401/test/Makefile
deleted file mode 100644 (file)
index d377f02..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-TOPDIR?=$(shell pwd)
-BOARD_DIR=$(TOPDIR)/../rtl
-CORES_DIR=$(TOPDIR)/../../../cores
-
-include ../sources.mak
-
-SIM_SRC=$(TOPDIR)/system_tb.v $(CORES_DIR)/hpdmc_ddr32/test/iddr.v $(CORES_DIR)/hpdmc_ddr32/test/oddr.v $(CORES_DIR)/hpdmc_ddr32/test/idelay.v
-
-SRC=$(SIM_SRC) $(BOARD_SRC) $(CORES_SRC)
-
-all: isim
-
-cversim: $(SRC) bios.rom
-       cver +define+SIMULATION +incdir+$(BOARD_DIR) +incdir+$(CORES_DIR)/lm32/rtl $(SRC)
-
-isim: system bios.rom
-       ./system
-
-system: $(SRC)
-       iverilog -D SIMULATION -I $(BOARD_DIR) -I $(CORES_DIR)/lm32/rtl -o system $(SRC)
-
-bios.rom: ../../../software/bios/bios.bin
-       ../../../tools/bin2hex ../../../software/bios/bios.bin bios.rom 32768
-
-clean:
-       rm -f verilog.log system
-
-.PHONY: clean cversim isim
diff --git a/boards/xilinx-ml401/test/system_tb.v b/boards/xilinx-ml401/test/system_tb.v
deleted file mode 100644 (file)
index 46e8f66..0000000
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`timescale 1ns/1ps
-
-module system_tb();
-
-reg sys_clk;
-reg resetin;
-
-initial sys_clk = 1'b0;
-always #5 sys_clk = ~sys_clk;
-
-initial begin
-       resetin = 1'b0;
-       #200 resetin = 1'b1;
-end
-
-wire [24:0] flash_adr;
-reg [31:0] flash_d;
-reg [31:0] flash[0:32767];
-initial $readmemh("bios.rom", flash);
-always @(flash_adr) #110 flash_d = flash[flash_adr/2];
-
-system system(
-       .clkin(sys_clk),
-       .resetin(resetin),
-
-       .flash_adr(flash_adr),
-       .flash_d(flash_d),
-
-       .uart_rxd(),
-       .uart_txd()
-);
-
-endmodule
index 08dda99..08bd897 100755 (executable)
@@ -18,7 +18,6 @@ cd $BASEDIR/software/libnet && make clean
 cd $BASEDIR/software/bios && make clean
 cd $BASEDIR/software/demo && make clean
 
-cd $BASEDIR/boards/xilinx-ml401/synthesis && make -f common.mak clean
 cd $BASEDIR/boards/milkymist-one/synthesis && make -f common.mak clean
 cd $BASEDIR/boards/milkymist-one/flash && make clean
 
@@ -32,4 +31,4 @@ cd $BASEDIR/cores/pfpu
 
 cd $BASEDIR
 
-rm -f tools.log software.log synthesis.log doc.log load.log biosflash.log bitflash.log
+rm -f tools.log software.log synthesis.log doc.log load.log
index 48a15d2..3e8aac4 100644 (file)
@@ -1 +1 @@
-COREDOC="ac97 aceusb conbus fmlbrg fmlmeter hpdmc_ddr32 minimac pfpu sysctl tmu2 uart vgafb"
+COREDOC="ac97 conbus fmlbrg fmlmeter hpdmc_ddr32 minimac pfpu sysctl tmu2 uart vgafb"
diff --git a/cores/aceusb/doc/Makefile b/cores/aceusb/doc/Makefile
deleted file mode 100644 (file)
index 9925ec9..0000000
+++ /dev/null
@@ -1,23 +0,0 @@
-TEX=aceusb.tex
-
-DVI=$(TEX:.tex=.dvi)
-PS=$(TEX:.tex=.ps)
-PDF=$(TEX:.tex=.pdf)
-AUX=$(TEX:.tex=.aux)
-LOG=$(TEX:.tex=.log)
-
-all: $(PDF)
-
-%.dvi: %.tex
-       latex $<
-
-%.ps: %.dvi
-       dvips $<
-
-%.pdf: %.ps
-       ps2pdf $<
-
-clean:
-       rm -f $(DVI) $(PS) $(PDF) $(AUX) $(LOG)
-
-.PHONY: clean
diff --git a/cores/aceusb/doc/aceusb.tex b/cores/aceusb/doc/aceusb.tex
deleted file mode 100644 (file)
index 6acd838..0000000
+++ /dev/null
@@ -1,40 +0,0 @@
-\documentclass[a4paper,11pt]{article}
-\usepackage{fullpage}
-\usepackage[latin1]{inputenc}
-\usepackage[T1]{fontenc}
-\usepackage[normalem]{ulem}
-\usepackage[english]{babel}
-\usepackage{listings,babel}
-\lstset{breaklines=true,basicstyle=\ttfamily}
-\usepackage{graphicx}
-\usepackage{moreverb}
-\usepackage{url}
-
-\title{Wishbone to SystemACE MPU interface bridge}
-\author{S\'ebastien Bourdeauducq}
-\date{December 2009}
-\begin{document}
-\setlength{\parindent}{0pt}
-\setlength{\parskip}{5pt}
-\maketitle{}
-\section{Specifications}
-This IP core bridges a Wishbone interface to the SystemACE MPU interface on the ML401 development board. The SystemACE chip must be used to access the CF card slot of the board.
-
-It maps the registers of this chip to the Wishbone address space, and takes care of resynchronizing the signals between the Wishbone and the on-board 30MHz clock domains.
-
-Accent has been put on simplicity and low resource usage rather than performance. With a 100MHz Wishbone clock, the write latency is typically 10 cycles, and the read latency 14 cycles.
-
-On the ML401, the core will disable the USB chip. The 16-bit SystemACE registers are mapped to the Wishbone bus, with each register expanded to 32 bits (the 16 most significant bits are always zero).
-
-The SystemACE registers are documented in Xilinx datasheet DS080.
-
-\section{Using the core}
-Connecting the core is very simple. The Wishbone signals are standard, and the other signals should go the the FPGA pads.
-
-Only attention should be paid to the clock signal. It must be generated externally (with the on-board oscillator on the ML401) and is an input to the core, and also to the FPGA in the ML401 case.
-
-\section*{Copyright notice}
-Copyright \copyright 2007-2009 S\'ebastien Bourdeauducq. \\
-Permission is granted to copy, distribute and/or modify this document under the terms of the GNU Free Documentation License, Version 1.3; with no Invariant Sections, no Front-Cover Texts, and no Back-Cover Texts. A copy of the license is included in the LICENSE.FDL file at the root of the Milkymist source distribution.
-
-\end{document}
diff --git a/cores/aceusb/doc/ds080.pdf b/cores/aceusb/doc/ds080.pdf
deleted file mode 100644 (file)
index 49a61c3..0000000
Binary files a/cores/aceusb/doc/ds080.pdf and /dev/null differ
diff --git a/cores/aceusb/rtl/aceusb.v b/cores/aceusb/rtl/aceusb.v
deleted file mode 100644 (file)
index 54674cb..0000000
+++ /dev/null
@@ -1,160 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module aceusb(
-       /* WISHBONE interface */
-       input sys_clk,
-       input sys_rst,
-       
-       input [31:0] wb_adr_i,
-       input [31:0] wb_dat_i,
-       output [31:0] wb_dat_o,
-       input wb_cyc_i,
-       input wb_stb_i,
-       input wb_we_i,
-       output reg wb_ack_o,
-
-       /* Signals shared between SystemACE and USB */
-       output [6:0] aceusb_a,
-       inout [15:0] aceusb_d,
-       output aceusb_oe_n,
-       output aceusb_we_n,
-
-       /* SystemACE signals */
-       input ace_clkin,
-       output ace_mpce_n,
-       input ace_mpirq,
-
-       output usb_cs_n,
-       output usb_hpi_reset_n,
-       input usb_hpi_int
-);
-
-wire access_read1;
-wire access_write1;
-wire access_ack1;
-
-/* Avoid potential glitches by sampling wb_adr_i and wb_dat_i only at the appropriate time */
-reg load_adr_dat;
-reg [5:0] address_reg;
-reg [15:0] data_reg;
-always @(posedge sys_clk) begin
-       if(load_adr_dat) begin
-               address_reg <= wb_adr_i[7:2];
-               data_reg <= wb_dat_i[15:0];
-       end
-end
-
-aceusb_access access(
-       .ace_clkin(ace_clkin),
-       .rst(sys_rst),
-       
-       .a(address_reg),
-       .di(data_reg),
-       .do(wb_dat_o[15:0]),
-       .read(access_read1),
-       .write(access_write1),
-       .ack(access_ack1),
-
-       .aceusb_a(aceusb_a),
-       .aceusb_d(aceusb_d),
-       .aceusb_oe_n(aceusb_oe_n),
-       .aceusb_we_n(aceusb_we_n),
-       .ace_mpce_n(ace_mpce_n),
-       .ace_mpirq(ace_mpirq),
-       .usb_cs_n(usb_cs_n),
-       .usb_hpi_reset_n(usb_hpi_reset_n),
-       .usb_hpi_int(usb_hpi_int)
-);
-
-assign wb_dat_o[31:16] = 16'h0000;
-
-/* Synchronize read, write and acknowledgement pulses */ 
-reg access_read;
-reg access_write;
-wire access_ack;
-
-aceusb_sync sync_read(
-       .clk0(sys_clk),
-       .flagi(access_read),
-       
-       .clk1(ace_clkin),
-       .flago(access_read1)
-);
-
-aceusb_sync sync_write(
-       .clk0(sys_clk),
-       .flagi(access_write),
-       
-       .clk1(ace_clkin),
-       .flago(access_write1)
-);
-
-aceusb_sync sync_ack(
-       .clk0(ace_clkin),
-       .flagi(access_ack1),
-       
-       .clk1(sys_clk),
-       .flago(access_ack)
-);
-
-/* Main FSM */
-
-reg state;
-reg next_state;
-
-parameter IDLE = 1'd0;
-parameter WAIT = 1'd1;
-
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               state <= IDLE;
-       else
-               state <= next_state;
-end
-
-always @(*) begin
-       load_adr_dat = 1'b0;
-       wb_ack_o = 1'b0;
-       access_read = 1'b0;
-       access_write = 1'b0;
-       
-       next_state = state;
-       
-       case(state)
-               IDLE: begin
-                       if(wb_cyc_i & wb_stb_i) begin
-                               load_adr_dat = 1'b1;
-                               if(wb_we_i)
-                                       access_write = 1'b1;
-                               else
-                                       access_read = 1'b1;
-                               next_state = WAIT;
-                       end
-               end
-               
-               WAIT: begin
-                       if(access_ack) begin
-                               wb_ack_o = 1'b1;
-                               next_state = IDLE;
-                       end
-               end
-       endcase
-end
-
-endmodule
\ No newline at end of file
diff --git a/cores/aceusb/rtl/aceusb_access.v b/cores/aceusb/rtl/aceusb_access.v
deleted file mode 100644 (file)
index e703d39..0000000
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module aceusb_access(
-       /* Control */
-       input ace_clkin,
-       input rst,
-       input [5:0] a,
-       input [15:0] di,
-       output reg [15:0] do,
-       input read,
-       input write,
-       output reg ack,
-
-       /* SystemACE/USB interface */
-       output [6:0] aceusb_a,
-       inout [15:0] aceusb_d,
-       output reg aceusb_oe_n,
-       output reg aceusb_we_n,
-
-       output reg ace_mpce_n,
-       input ace_mpirq,
-
-       output usb_cs_n,
-       output usb_hpi_reset_n,
-       input usb_hpi_int
-);
-
-/* USB is not supported yet. Disable the chip. */
-assign usb_cs_n = 1'b1;
-assign usb_hpi_reset_n = 1'b1;
-
-/* 16-bit mode only */
-assign aceusb_a = {a, 1'b0};
-
-reg d_drive;
-assign aceusb_d = d_drive ? di : 16'hzz;
-
-reg d_drive_r;
-reg aceusb_oe_n_r;
-reg aceusb_we_n_r;
-reg ace_mpce_n_r;
-always @(posedge ace_clkin) begin
-       d_drive <= d_drive_r;
-       aceusb_oe_n <= aceusb_oe_n_r;
-       aceusb_we_n <= aceusb_we_n_r;
-       ace_mpce_n <= ace_mpce_n_r;
-end
-
-reg d_in_sample;
-always @(posedge ace_clkin)
-       if(d_in_sample)
-               do <= aceusb_d;
-
-reg [2:0] state;
-reg [2:0] next_state;
-
-localparam
-       IDLE = 3'd0,
-       READ = 3'd1,
-       READ1 = 3'd2,
-       READ2 = 3'd3,
-       WRITE = 3'd4,
-       ACK = 3'd5;
-
-always @(posedge ace_clkin) begin
-       if(rst)
-               state <= IDLE;
-       else
-               state <= next_state;
-end
-
-always @(*) begin
-       d_drive_r = 1'b0;
-       aceusb_oe_n_r = 1'b1;
-       aceusb_we_n_r = 1'b1;
-       ace_mpce_n_r = 1'b1;
-       d_in_sample = 1'b0;
-       ack = 1'b0;
-       
-       next_state = state;
-       
-       case(state)
-               IDLE: begin
-                       if(read) begin
-                               ace_mpce_n_r = 1'b0;
-                               next_state = READ;
-                       end
-                       if(write) begin
-                               ace_mpce_n_r = 1'b0;
-                               next_state = WRITE;
-                       end
-               end
-               
-               READ: begin
-                       ace_mpce_n_r = 1'b0;
-                       next_state = READ1;
-               end
-               READ1: begin
-                       ace_mpce_n_r = 1'b0;
-                       aceusb_oe_n_r = 1'b0;
-                       next_state = READ2;
-               end
-               READ2: begin
-                       d_in_sample = 1'b1;
-                       next_state = ACK;
-               end
-               
-               WRITE: begin
-                       d_drive_r = 1'b1;
-                       ace_mpce_n_r = 1'b0;
-                       aceusb_we_n_r = 1'b0;
-                       next_state = ACK;
-               end
-               
-               ACK: begin
-                       ack = 1'b1;
-                       next_state = IDLE;
-               end
-       endcase
-end
-
-endmodule
diff --git a/cores/aceusb/rtl/aceusb_sync.v b/cores/aceusb/rtl/aceusb_sync.v
deleted file mode 100644 (file)
index 868c4d6..0000000
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-/* Flag synchronizer from clock domain 0 to 1
- * See http://www.fpga4fun.com/CrossClockDomain.html
- */
-
-module aceusb_sync(
-       input clk0,
-       input flagi,
-       
-       input clk1,
-       output flago
-);
-
-/* Turn the flag into a level change */
-reg toggle;
-initial toggle = 1'b0;
-always @(posedge clk0)
-       if(flagi) toggle <= ~toggle;
-
-/* Synchronize the level change to clk1.
- * We add a third flip-flop to be able to detect level changes. */
-reg [2:0] sync;
-initial sync = 3'b000;
-always @(posedge clk1)
-       sync <= {sync[1:0], toggle};
-
-/* Recreate the flag from the level change into the clk1 domain */
-assign flago = sync[2] ^ sync[1];
-
-endmodule
diff --git a/cores/aceusb/test/Makefile b/cores/aceusb/test/Makefile
deleted file mode 100644 (file)
index 048a79b..0000000
+++ /dev/null
@@ -1,17 +0,0 @@
-SOURCES=tb_aceusb.v $(wildcard ../rtl/*.v)
-
-all: tb_aceusb
-
-isim: tb_aceusb
-       ./tb_aceusb
-
-cversim: $(SOURCES)
-       cver $(SOURCES)
-
-clean:
-       rm -f tb_aceusb verilog.log aceusb.vcd
-
-tb_aceusb: $(SOURCES)
-       iverilog -o tb_aceusb $(SOURCES)
-
-.PHONY: clean sim cversim
diff --git a/cores/aceusb/test/tb_aceusb.v b/cores/aceusb/test/tb_aceusb.v
deleted file mode 100644 (file)
index 028521c..0000000
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * Milkymist VJ SoC
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-`timescale 1ns / 1ps
-
-module tb_aceusb();
-
-reg sys_clk;
-reg sys_rst;
-reg ace_clk;
-
-reg [31:0] wb_adr_i;
-reg [31:0] wb_dat_i;
-wire [31:0] wb_dat_o;
-reg wb_cyc_i;
-reg wb_stb_i;
-reg wb_we_i;
-wire wb_ack_o;
-
-wire [6:0] aceusb_a;
-wire [15:0] aceusb_d;
-wire aceusb_oe_n;
-wire aceusb_we_n;
-wire ace_clkin;
-wire ace_mpce_n;
-wire ace_mpirq;
-wire usb_cs_n;
-wire usb_hpi_reset_n;
-wire usb_hpi_int;
-
-aceusb dut(
-       .sys_clk(sys_clk),
-       .sys_rst(sys_rst),
-
-       .wb_adr_i(wb_adr_i),
-       .wb_dat_i(wb_dat_i),
-       .wb_dat_o(wb_dat_o),
-       .wb_cyc_i(wb_cyc_i),
-       .wb_stb_i(wb_stb_i),
-       .wb_we_i(wb_we_i),
-       .wb_ack_o(wb_ack_o),
-
-       .aceusb_a(aceusb_a),
-       .aceusb_d(aceusb_d),
-       .aceusb_oe_n(aceusb_oe_n),
-       .aceusb_we_n(aceusb_we_n),
-       .ace_clkin(ace_clk),
-       .ace_mpce_n(ace_mpce_n),
-       .ace_mpirq(ace_mpirq),
-       .usb_cs_n(usb_cs_n),
-       .usb_hpi_reset_n(usb_hpi_reset_n),
-       .usb_hpi_int(usb_hpi_int)
-);
-
-assign aceusb_d = aceusb_oe_n ? 16'h1234 : 16'hzzzz;
-
-initial begin
-       $dumpfile("aceusb.vcd");
-       $dumpvars(1, dut);
-end
-
-/* Generate ~33MHz SystemACE clock */
-initial ace_clk <= 0;
-always #7.5 ace_clk <= ~ace_clk;
-
-task wbwrite;
-       input [31:0] address;
-       input [31:0] data;
-       integer i;
-       begin
-               wb_adr_i = address;
-               wb_dat_i = data;
-               wb_cyc_i = 1'b1;
-               wb_stb_i = 1'b1;
-               wb_we_i = 1'b1;
-               
-               i = 1;
-               while(~wb_ack_o) begin
-                       #5 sys_clk = 1'b1;
-                       #5 sys_clk = 1'b0;
-                       i = i + 1;
-               end
-               
-               $display("Write address %h completed in %d cycles", address, i);
-               
-               /* Let the core release its ack */
-               #5 sys_clk = 1'b1;
-               #5 sys_clk = 1'b0;
-               
-               wb_we_i = 1'b1;
-               wb_cyc_i = 1'b0;
-               wb_stb_i = 1'b0;
-       end
-endtask
-
-task wbread;
-       input [31:0] address;
-       integer i;
-       begin
-               wb_adr_i = address;
-               wb_cyc_i = 1'b1;
-               wb_stb_i = 1'b1;
-               wb_we_i = 1'b0;
-               
-               i = 1;
-               while(~wb_ack_o) begin
-                       #5 sys_clk = 1'b1;
-                       #5 sys_clk = 1'b0;
-                       i = i + 1;
-               end
-               
-               $display("Read address %h completed in %d cycles, result %h", address, i, wb_dat_o);
-               
-               /* Let the core release its ack */
-               #5 sys_clk = 1'b1;
-               #5 sys_clk = 1'b0;
-               
-               wb_cyc_i = 1'b0;
-               wb_stb_i = 1'b0;
-       end
-endtask
-
-initial begin
-       sys_rst = 1'b1;
-       sys_clk = 1'b0;
-       
-       wb_adr_i = 32'h00000000;
-       wb_dat_i = 32'h00000000;
-       wb_cyc_i = 1'b0;
-       wb_stb_i = 1'b0;
-       wb_we_i = 1'b0;
-
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       #5 sys_clk = 1'b1;
-       #5 sys_clk = 1'b0;
-       
-       sys_rst = 1'b0;
-       
-       wbwrite(32'h00000180, 32'hcafebabe);
-       wbread(32'h00000020);
-       
-       $finish;
-end
-
-endmodule
-
diff --git a/cores/ps2/rtl/ps2.v b/cores/ps2/rtl/ps2.v
deleted file mode 100644 (file)
index 1dbcc6f..0000000
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * PS2 Interface
- * Copyright (C) 2009 Takeshi Matsuya
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-module ps2 #(
-       parameter csr_addr = 4'h0,
-       parameter clk_freq = 100000000
-) (
-       input sys_rst,
-       input sys_clk,
-
-       input [13:0] csr_a,
-       input csr_we,
-       input [31:0] csr_di,
-       output reg [31:0] csr_do,
-
-       inout ps2_clk,
-       inout ps2_data,
-       output reg irq
-);
-
-/* CSR interface */
-wire csr_selected = csr_a[13:10] == csr_addr;
-reg tx_busy;
-
-//-----------------------------------------------------------------
-// divisor
-//-----------------------------------------------------------------
-reg [9:0] enable_counter;
-wire enable;
-assign enable = (enable_counter == 10'd0);
-
-parameter divisor = clk_freq/12800/16;
-
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               enable_counter <= divisor - 10'd1;
-       else begin
-               enable_counter <= enable_counter - 10'd1;
-               if(enable)
-                       enable_counter <= divisor - 10'd1;
-       end
-end
-
-//-----------------------------------------------------------------
-// Synchronize ps2 clock and data
-//-----------------------------------------------------------------
-reg ps2_clk_1;
-reg ps2_data_1;
-reg ps2_clk_2;
-reg ps2_data_2;
-reg ps2_clk_out;
-reg ps2_data_out1, ps2_data_out2;
-
-always @(posedge sys_clk) begin
-       ps2_clk_1 <= ps2_clk;
-       ps2_data_1 <= ps2_data;
-       ps2_clk_2 <= ps2_clk_1;
-       ps2_data_2 <= ps2_data_1;
-end
-
-/* PS2 */
-reg [7:0] kcode;
-reg rx_clk_data;
-reg [5:0] rx_clk_count;
-reg [4:0] rx_bitcount;
-reg [10:0] rx_data;
-reg [10:0] tx_data;
-reg we_reg;
-
-/* FSM */
-reg [2:0] state;
-reg [2:0] next_state;
-
-parameter RECEIVE              = 3'd0;
-parameter WAIT_READY           = 3'd1;
-parameter CLOCK_LOW            = 3'd2;
-parameter CLOCK_HIGH           = 3'd3;
-parameter CLOCK_HIGH1          = 3'd4;
-parameter CLOCK_HIGH2          = 3'd5;
-parameter WAIT_CLOCK_LOW       = 3'd6;
-parameter TRANSMIT             = 3'd7;
-
-assign state_receive = state == RECEIVE;
-assign state_transmit = state == TRANSMIT;
-
-always @(posedge sys_clk) begin
-       if(sys_rst)
-               state = RECEIVE;
-       else begin
-               state = next_state;
-       end
-end
-
-/* ps2 clock falling edge 100us counter */
-//parameter divisor_100us = clk_freq/10000;
-parameter divisor_100us = 1;
-reg [16:0] watchdog_timer;
-wire watchdog_timer_done;
-assign watchdog_timer_done = (watchdog_timer == 17'd0);
-always @(posedge sys_clk) begin
-       if(sys_rst||ps2_clk_out)
-               watchdog_timer <= divisor_100us - 1;
-       else if(~watchdog_timer_done)
-                       watchdog_timer <= watchdog_timer - 1;
-end
-
-always @(*) begin
-       ps2_clk_out = 1'b1;
-       ps2_data_out1 = 1'b1;
-       tx_busy = 1'b1;
-
-       next_state = state;
-
-       case(state)
-               RECEIVE: begin
-                       tx_busy = 1'b0;
-                       if(we_reg) begin
-                               next_state = WAIT_READY;
-                       end
-               end
-               WAIT_READY: begin
-                       if(rx_bitcount == 5'd0) begin
-                               ps2_clk_out = 1'b0;
-                               next_state = CLOCK_LOW;
-                       end
-               end
-               CLOCK_LOW: begin
-                       ps2_clk_out = 1'b0;
-                       if(watchdog_timer_done) begin
-                               next_state = CLOCK_HIGH;
-                       end
-               end
-               CLOCK_HIGH: begin
-                       next_state = CLOCK_HIGH1;
-               end
-               CLOCK_HIGH1: begin
-                       next_state = CLOCK_HIGH2;
-               end
-               CLOCK_HIGH2: begin
-                       ps2_data_out1 = 1'b0;
-                       next_state = WAIT_CLOCK_LOW;
-               end
-               WAIT_CLOCK_LOW: begin
-                       ps2_data_out1 = 1'b0;
-                       if(ps2_clk_2 == 1'b0) begin
-                               next_state = TRANSMIT;
-                       end
-               end
-               TRANSMIT: begin
-                       if(rx_bitcount == 5'd10) begin
-                               next_state = RECEIVE;
-                       end
-               end
-       endcase
-end
-
-//-----------------------------------------------------------------
-// PS2 RX/TX Logic
-//-----------------------------------------------------------------
-always @(posedge sys_clk) begin
-       if(sys_rst) begin
-               rx_clk_data <= 1'd1;
-               rx_clk_count <= 5'd0;
-               rx_bitcount <= 5'd0;
-               rx_data <= 11'b11111111111;
-               irq <= 1'd0;
-               csr_do <= 32'd0;
-               we_reg <= 1'b0;
-               ps2_data_out2 <= 1'b1;
-       end else begin
-               irq <= 1'b0;
-               we_reg <= 1'b0;
-               csr_do <= 32'd0;
-               if(csr_selected) begin
-                       case(csr_a[0])
-                               1'b0: csr_do <= kcode;
-                               1'b1: csr_do <= tx_busy;
-                       endcase
-                       if(csr_we && csr_a[0] == 1'b0) begin
-                               tx_data <= {2'b11, ~(^csr_di[7:0]), csr_di[7:0]}; // STOP+PARITY+DATA
-                               we_reg <= 1'b1;
-                       end
-               end
-               if(enable) begin
-                       if(rx_clk_data == ps2_clk_2) begin
-                               rx_clk_count <= rx_clk_count + 5'd1;
-                       end else begin
-                               rx_clk_count <= 5'd0;
-                               rx_clk_data <= ps2_clk_2;
-                       end
-                       if(state_receive && rx_clk_data == 1'b0 && rx_clk_count == 5'd4) begin
-                               rx_data <= {ps2_data_2, rx_data[10:1]};
-                               rx_bitcount <= rx_bitcount + 5'd1;
-                               if(rx_bitcount == 5'd10) begin
-                                       irq <= 1'b1;
-                                       kcode <= rx_data[9:2];
-                               end
-                       end
-                       if(state_transmit && rx_clk_data == 1'b0 && rx_clk_count == 5'd0) begin
-                               ps2_data_out2 <= tx_data[rx_bitcount];
-                               rx_bitcount <= rx_bitcount + 5'd1;
-                               if(rx_bitcount == 5'd10) begin
-                                       ps2_data_out2 <= 1'b1;
-                               end
-                       end
-                       if(rx_clk_count == 5'd16) begin
-                               rx_bitcount <= 5'd0;
-                               rx_data <= 11'b11111111111;
-                       end
-               end
-       end
-end
-
-assign ps2_clk = ps2_clk_out ? 1'hz : 1'b0;
-assign ps2_data = ps2_data_out1 & ps2_data_out2 ? 1'hz : 1'b0;
-
-endmodule
index d090a89..52ba29a 100644 (file)
@@ -42,8 +42,7 @@ boot.o: ../../software/include/base/stdlib.h
 boot.o: ../../software/include/base/console.h
 boot.o: ../../software/include/base/uart.h
 boot.o: ../../software/include/base/system.h
-boot.o: ../../software/include/base/board.h
-boot.o: ../../software/include/base/cffat.h ../../software/include/base/crc.h
+boot.o: ../../software/include/base/board.h ../../software/include/base/crc.h
 boot.o: ../../tools/sfl.h ../../software/include/net/microudp.h
 boot.o: ../../software/include/net/tftp.h ../../software/include/hw/hpdmc.h
 boot.o: ../../software/include/hw/common.h boot.h
@@ -52,7 +51,7 @@ main.o: ../../software/include/base/stdlib.h
 main.o: ../../software/include/base/console.h
 main.o: ../../software/include/base/string.h
 main.o: ../../software/include/base/uart.h
-main.o: ../../software/include/base/cffat.h ../../software/include/base/crc.h
+main.o: ../../software/include/base/fatfs.h ../../software/include/base/crc.h
 main.o: ../../software/include/base/system.h
 main.o: ../../software/include/base/board.h
 main.o: ../../software/include/base/version.h
index 0007c42..36f0797 100644 (file)
@@ -20,7 +20,6 @@
 #include <uart.h>
 #include <system.h>
 #include <board.h>
-#include <cffat.h>
 #include <crc.h>
 #include <sfl.h>
 
@@ -260,63 +259,7 @@ void netboot()
        boot(cmdline_adr, initrdstart_adr, initrdend_adr, SDRAM_BASE);
 }
 
-static int tryload(char *filename, unsigned int address)
-{
-       int devsize, realsize;
-       
-       devsize = cffat_load(filename, (char *)address, 16*1024*1024, &realsize);
-       if(devsize <= 0)
-               return -1;
-       if(realsize > devsize) {
-               printf("E: File size larger than the blocks read (corrupted FS or IO error ?)\n");
-               cffat_done();
-               return -1;
-       }
-       printf("I: Read a %d byte image from %s\n", realsize, filename);
-       
-       return realsize;
-}
-
-
 void cardboot(int alt)
 {
-       int size;
-       unsigned int cmdline_adr, initrdstart_adr, initrdend_adr;
-
-       if(brd_desc->memory_card == MEMCARD_NONE) {
-               printf("E: No memory card on this board\n");
-               return;
-       }
-       
-       printf("I: Booting from CF card...\n");
-       if(!cffat_init()) {
-               printf("E: Unable to initialize filesystem\n");
-               return;
-       }
-
-       if(tryload(alt ? "ALTBOOT.BIN" : "BOOT.BIN", SDRAM_BASE) <= 0) {
-               printf("E: Firmware image not found\n");
-               return;
-       }
-
-       cmdline_adr = SDRAM_BASE+0x1000000;
-       size = tryload("CMDLINE.TXT", cmdline_adr);
-       if(size <= 0) {
-               printf("I: No command line parameters found (CMDLINE.TXT)\n");
-               cmdline_adr = 0;
-       } else
-               *((char *)(cmdline_adr+size)) = 0x00;
-
-       initrdstart_adr = SDRAM_BASE+0x1002000;
-       size = tryload("INITRD.BIN", initrdstart_adr);
-       if(size <= 0) {
-               printf("I: No initial ramdisk found (INITRD.BIN)\n");
-               initrdstart_adr = 0;
-               initrdend_adr = 0;
-       } else
-               initrdend_adr = initrdstart_adr + size - 1;
-
-       cffat_done();
-       printf("I: Booting...\n");
-       boot(cmdline_adr, initrdstart_adr, initrdend_adr, SDRAM_BASE);
+       printf("FIXME: memory card boot is not implemented\n");
 }
index 75a301b..8acdbee 100644 (file)
@@ -19,7 +19,7 @@
 #include <console.h>
 #include <string.h>
 #include <uart.h>
-#include <cffat.h>
+#include <fatfs.h>
 #include <crc.h>
 #include <system.h>
 #include <board.h>
@@ -209,13 +209,9 @@ static int lscb(const char *filename, const char *longname, void *param)
 
 static void ls()
 {
-       if(brd_desc->memory_card == MEMCARD_NONE) {
-               printf("E: No memory card on this board\n");
-               return;
-       }
-       cffat_init();
-       cffat_list_files(lscb, NULL);
-       cffat_done();
+       fatfs_init();
+       fatfs_list_files(lscb, NULL);
+       fatfs_done();
 }
 
 static void load(char *filename, char *addr)
@@ -223,11 +219,6 @@ static void load(char *filename, char *addr)
        char *c;
        unsigned int *addr2;
 
-       if(brd_desc->memory_card == MEMCARD_NONE) {
-               printf("E: No memory card on this board\n");
-               return;
-       }
-
        if((*filename == 0) || (*addr == 0)) {
                printf("load <filename> <address>\n");
                return;
@@ -237,9 +228,9 @@ static void load(char *filename, char *addr)
                printf("incorrect address\n");
                return;
        }
-       cffat_init();
-       cffat_load(filename, (char *)addr2, 16*1024*1024, NULL);
-       cffat_done();
+       fatfs_init();
+       fatfs_load(filename, (char *)addr2, 16*1024*1024, NULL);
+       fatfs_done();
 }
 
 static void mdior(char *reg)
@@ -413,12 +404,10 @@ static void display_capabilities()
        unsigned int cap;
 
        cap = CSR_CAPABILITIES;
-       display_capability("SystemACE ", cap & CAP_SYSTEMACE);
+       display_capability("Mem. card ", cap & CAP_MEMORYCARD);
        display_capability("AC'97     ", cap & CAP_AC97);
        display_capability("PFPU      ", cap & CAP_PFPU);
        display_capability("TMU       ", cap & CAP_TMU);
-       display_capability("PS/2 Kbd  ", cap & CAP_PS2_KEYBOARD);
-       display_capability("PS/2 Mouse", cap & CAP_PS2_MOUSE);
        display_capability("Ethernet  ", cap & CAP_ETHERNET);
        display_capability("FML Meter ", cap & CAP_FMLMETER);
 }
@@ -436,12 +425,10 @@ static void boot_sequence()
        if(test_user_abort()) {
                serialboot(1);
                netboot();
-               if(brd_desc->memory_card != MEMCARD_NONE) {
-                       if(CSR_GPIO_IN & GPIO_DIP1)
-                               cardboot(1);
-                       else
-                               cardboot(0);
-               }
+               if(CSR_GPIO_IN & GPIO_BTN1)
+                       cardboot(1);
+               else
+                       cardboot(0);
                printf("E: No boot medium found\n");
        }
 }
@@ -454,7 +441,7 @@ int main(int i, char **c)
 
        /* Check for double baud rate */
        if(brd_desc != NULL) {
-               if(CSR_GPIO_IN & GPIO_DIP2)
+               if(CSR_GPIO_IN & GPIO_BTN2)
                        CSR_UART_DIVISOR = brd_desc->clk_frequency/230400/16;
        }
 
index 1469952..0ee82aa 100644 (file)
@@ -110,7 +110,7 @@ shell.o: ../../software/include/base/stdlib.h
 shell.o: ../../software/include/base/string.h
 shell.o: ../../software/include/base/console.h
 shell.o: ../../software/include/base/uart.h
-shell.o: ../../software/include/base/cffat.h
+shell.o: ../../software/include/base/fatfs.h
 shell.o: ../../software/include/base/system.h
 shell.o: ../../software/include/base/math.h ../../software/include/base/irq.h
 shell.o: ../../software/include/base/board.h ../../software/include/hw/pfpu.h
index 1f0615d..1283d60 100644 (file)
@@ -20,7 +20,7 @@
 #include <string.h>
 #include <console.h>
 #include <uart.h>
-#include <cffat.h>
+#include <fatfs.h>
 #include <system.h>
 #include <math.h>
 #include <irq.h>
@@ -154,9 +154,9 @@ static int lscb(const char *filename, const char *longname, void *param)
 
 static void ls()
 {
-       cffat_init();
-       cffat_list_files(lscb, NULL);
-       cffat_done();
+       fatfs_init();
+       fatfs_list_files(lscb, NULL);
+       fatfs_done();
 }
 
 static void render(const char *filename)
@@ -257,9 +257,9 @@ static void loadpic(const char *filename)
                return;
        }
 
-       if(!cffat_init()) return;
-       if(!cffat_load(filename, (void *)vga_backbuffer, vga_hres*vga_vres*2, &size)) return;
-       cffat_done();
+       if(!fatfs_init()) return;
+       if(!fatfs_load(filename, (void *)vga_backbuffer, vga_hres*vga_vres*2, &size)) return;
+       fatfs_done();
 
        vga_swap_buffers();
 }
@@ -413,117 +413,6 @@ static void tmutest()
        vga_swap_buffers();
 }
 
-static unsigned short original[640*480*2] __attribute__((aligned(2)));
-
-static void tmudemo()
-{
-       int size;
-       static struct tmu_vertex srcmesh[TMU_MESH_MAXSIZE][TMU_MESH_MAXSIZE] __attribute__((aligned(8)));
-       struct tmu_td td;
-       volatile int complete;
-       int w, speed;
-       int mindelta, xdelta, ydelta;
-
-       if(!cffat_init()) return;
-       if(!cffat_load("lena.raw", (void *)original, vga_hres*vga_vres*2, &size)) return;
-       cffat_done();
-
-       printf("done\n");
-       
-       speed = 0;
-       w = 512 << TMU_FIXEDPOINT_SHIFT;
-
-       xdelta = 0;
-       ydelta = 0;
-       while(1) {
-               srcmesh[0][0].x = xdelta;
-               srcmesh[0][0].y = ydelta;
-               srcmesh[0][1].x = w+xdelta;
-               srcmesh[0][1].y = ydelta;
-               srcmesh[1][0].x = xdelta;
-               srcmesh[1][0].y = w+ydelta;
-               srcmesh[1][1].x = w+xdelta;
-               srcmesh[1][1].y = w+ydelta;
-
-               if(CSR_GPIO_IN & GPIO_DIP6) {
-                       if(CSR_GPIO_IN & GPIO_PBN)
-                               ydelta += 16;
-                       if(CSR_GPIO_IN & GPIO_PBS)
-                               ydelta -= 16;
-                       if(CSR_GPIO_IN & GPIO_PBE)
-                               xdelta += 16;
-                       if(CSR_GPIO_IN & GPIO_PBW)
-                               xdelta -= 16;
-               } else {
-                       if(CSR_GPIO_IN & GPIO_PBN)
-                               speed += 2;
-                       if(CSR_GPIO_IN & GPIO_PBS)
-                               speed -= 2;
-               }
-               w += speed;
-               if(w < 1) {
-                       w = 1;
-                       speed = 0;
-               }
-               if(xdelta > ydelta)
-                       mindelta = ydelta;
-               else
-                       mindelta = xdelta;
-               if(w > ((TMU_MASK_FULL >> 1)+mindelta)) {
-                       w = (TMU_MASK_FULL >> 1)+mindelta;
-                       speed = 0;
-               }
-               if(speed > 0) speed--;
-               if(speed < 0) speed++;
-               
-
-               td.flags = 0;
-               td.hmeshlast = 1;
-               td.vmeshlast = 1;
-               td.brightness = TMU_BRIGHTNESS_MAX;
-               td.chromakey = 0;
-               td.vertices = &srcmesh[0][0];
-               td.texfbuf = original;
-               td.texhres = vga_hres;
-               td.texvres = vga_vres;
-               td.texhmask = CSR_GPIO_IN & GPIO_DIP7 ? 0x7FFF : TMU_MASK_FULL;
-               td.texvmask = CSR_GPIO_IN & GPIO_DIP8 ? 0x7FFF : TMU_MASK_FULL;
-               td.dstfbuf = vga_backbuffer;
-               td.dsthres = vga_hres;
-               td.dstvres = vga_vres;
-               td.dsthoffset = 0;
-               td.dstvoffset = 0;
-               td.dstsquarew = vga_hres;
-               td.dstsquareh = vga_vres;
-               td.alpha = TMU_ALPHA_MAX;
-
-               td.callback = tmutest_callback;
-               td.user = (void *)&complete;
-
-               complete = 0;
-               flush_bridge_cache();
-               CSR_TIMER1_CONTROL = 0;
-               CSR_TIMER1_COUNTER = 0;
-               CSR_TIMER1_COMPARE = 0xffffffff;
-               CSR_TIMER1_CONTROL = TIMER_ENABLE;
-               tmu_submit_task(&td);
-               while(!complete);
-               CSR_TIMER1_CONTROL = 0;
-
-               if(readchar_nonblock()) {
-                       char c;
-                       c = readchar();
-                       if(c == 'q') break;
-                       if(c == 's') {
-                               unsigned int t;
-                               t = CSR_TIMER1_COUNTER;
-                               printf("Processing cycles: %d (%d Mpixels/s)\n", t, 640*480*100/t);
-                       }
-               }
-               vga_swap_buffers();
-       }
-}
-
 static void tmubench()
 {
        unsigned int oldmask;
@@ -690,7 +579,6 @@ static void do_command(char *c)
                else if(strcmp(command, "checker") == 0) checker();
                else if(strcmp(command, "pfputest") == 0) pfputest();
                else if(strcmp(command, "tmutest") == 0) tmutest();
-               else if(strcmp(command, "tmudemo") == 0) tmudemo();
                else if(strcmp(command, "tmubench") == 0) tmubench();
                else if(strcmp(command, "echo") == 0) echo();
 
index 9c28ab8..5f56dd2 100644 (file)
 
 #define BOARD_NAME_LEN 32
 
-enum {
-       MEMCARD_NONE,
-       MEMCARD_SYSTEMACE,
-       MEMCARD_MICROSD
-};
-
 struct board_desc {
        unsigned int id;
        char name[BOARD_NAME_LEN];
        unsigned int clk_frequency;
        unsigned int sdram_size;
-       unsigned int ddr_clkphase;
-       unsigned int ddr_idelay;
-       unsigned int ddr_dqsdelay;
-       unsigned int memory_card;
        unsigned int ethernet_phyadr;
 };
 
diff --git a/software/include/base/cfcard.h b/software/include/base/cfcard.h
deleted file mode 100644 (file)
index 8605c28..0000000
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- * 
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __CFCARD_H
-#define __CFCARD_H
-
-#define CF_BLOCK_SIZE  512
-
-int cf_init();
-int cf_readblock(unsigned int blocknr, unsigned char *buf);
-void cf_done();
-
-#endif /* __CFCARD_H */
diff --git a/software/include/base/cffat.h b/software/include/base/cffat.h
deleted file mode 100644 (file)
index 1d7faa8..0000000
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- * 
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __CFFAT_H
-#define __CFFAT_H
-
-typedef int (*cffat_dir_callback)(const char *, const char *, void *);
-
-int cffat_init();
-int cffat_list_files(cffat_dir_callback cb, void *param);
-int cffat_load(const char *filename, char *buffer, int size, int *realsize);
-void cffat_done();
-
-#endif /* __CFFAT_H */
diff --git a/software/include/base/fatfs.h b/software/include/base/fatfs.h
new file mode 100644 (file)
index 0000000..f8b71ba
--- /dev/null
@@ -0,0 +1,28 @@
+/*
+ * Milkymist VJ SoC (Software)
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ * 
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ * 
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef __FATFS_H
+#define __FATFS_H
+
+typedef int (*fatfs_dir_callback)(const char *, const char *, void *);
+
+int fatfs_init();
+int fatfs_list_files(fatfs_dir_callback cb, void *param);
+int fatfs_load(const char *filename, char *buffer, int size, int *realsize);
+void fatfs_done();
+
+#endif /* __FATFS_H */
index 2a62a55..ae74761 100644 (file)
 #ifndef __HW_CAPABILITIES
 #define __HW_CAPABILITIES
 
-#define CAP_SYSTEMACE          (0x00000001)
+#define CAP_MEMORYCARD         (0x00000001)
 #define CAP_AC97               (0x00000002)
 #define CAP_PFPU               (0x00000004)
 #define CAP_TMU                        (0x00000008)
-#define CAP_PS2_KEYBOARD       (0x00000010)
-#define CAP_PS2_MOUSE          (0x00000020)
-#define CAP_ETHERNET           (0x00000040)
-#define CAP_FMLMETER           (0x00000080)
+#define CAP_ETHERNET           (0x00000010)
+#define CAP_FMLMETER           (0x00000020)
 
 #endif /* __HW_CAPABILITIES */
index 6e801fb..c68fcf5 100644 (file)
@@ -1,6 +1,6 @@
 /*
  * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
  *
  * This program is free software: you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
 #define __HW_GPIO_H
 
 /* Inputs */
-#define GPIO_PBN       (0x00000001)
-#define GPIO_PBW       (0x00000002)
-#define GPIO_PBS       (0x00000004)
-#define GPIO_PBE       (0x00000008)
-#define GPIO_PBC       (0x00000010)
-
-#define GPIO_DIP1      (0x00000020)
-#define GPIO_DIP2      (0x00000040)
-#define GPIO_DIP3      (0x00000080)
-#define GPIO_DIP4      (0x00000100)
-#define GPIO_DIP5      (0x00000200)
-#define GPIO_DIP6      (0x00000400)
-#define GPIO_DIP7      (0x00000800)
-#define GPIO_DIP8      (0x00001000)
+#define GPIO_BTN1      (0x00000001)
+#define GPIO_BTN2      (0x00000002)
+#define GPIO_BTN3      (0x00000004)
 
 /* Outputs */
-#define GPIO_LED2      (0x00000001)
-#define GPIO_LED3      (0x00000002)
-
-#define GPIO_LEDN      (0x00000004)
-#define GPIO_LEDW      (0x00000008)
-#define GPIO_LEDS      (0x00000010)
-#define GPIO_LEDE      (0x00000020)
-#define GPIO_LEDC      (0x00000040)
-
-#define GPIO_HDLCDE    (0x00000080)
-#define GPIO_HDLCDRS   (0x00000100)
-#define GPIO_HDLCDRW   (0x00000200)
-
-#define GPIO_HDLCDD_SHIFT      (10)
-
-#define GPIO_HDLCDD4   (0x00000400)
-#define GPIO_HDLCDD5   (0x00000800)
-#define GPIO_HDLCDD6   (0x00001000)
-#define GPIO_HDLCDD7   (0x00002000)
+#define GPIO_LED1      (0x00000001)
+#define GPIO_LED2      (0x00000002)
 
 #endif /* __HW_GPIO_H */
index f8cc5d7..de0cf3e 100644 (file)
@@ -29,9 +29,7 @@
 #define IRQ_AC97DMAW           (0x00000100) /* 8 */
 #define IRQ_PFPU               (0x00000200) /* 9 */
 #define IRQ_TMU                        (0x00000400) /* 10 */
-#define IRQ_PS2KEYBOARD                (0x00000800) /* 11 */
-#define IRQ_PS2MOUSE           (0x00001000) /* 12 */
-#define IRQ_ETHRX              (0x00002000) /* 13 */
-#define IRQ_ETHTX              (0x00004000) /* 14 */
+#define IRQ_ETHRX              (0x00000800) /* 13 */
+#define IRQ_ETHTX              (0x00001000) /* 14 */
 
 #endif /* __INTERRUPTS_H */
diff --git a/software/include/hw/systemace.h b/software/include/hw/systemace.h
deleted file mode 100644 (file)
index 37f1805..0000000
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#ifndef __HW_SYSTEMACE_H
-#define __HW_SYSTEMACE_H
-
-#include <hw/common.h>
-
-#define CSR_ACE_BUSMODE                MMPTR(0xa0000000)
-#define CSR_ACE_STATUSL                MMPTR(0xa0000008)
-#define CSR_ACE_STATUSH                MMPTR(0xa000000C)
-#define CSR_ACE_ERRORL         MMPTR(0xa0000010)
-#define CSR_ACE_ERRORH         MMPTR(0xa0000014)
-#define CSR_ACE_CLBAL          MMPTR(0xa0000018)
-#define CSR_ACE_CLBAH          MMPTR(0xa000001C)
-#define CSR_ACE_MLBAL          MMPTR(0xa0000020)
-#define CSR_ACE_MLBAH          MMPTR(0xa0000024)
-#define CSR_ACE_SECCMD         MMPTR(0xa0000028)
-#define CSR_ACE_VERSION                MMPTR(0xa000002C)
-#define CSR_ACE_CTLL           MMPTR(0xa0000030)
-#define CSR_ACE_CTLH           MMPTR(0xa0000034)
-#define CSR_ACE_FAT            MMPTR(0xa0000038)
-#define CSR_ACE_DATA           MMPTR(0xa0000080)
-
-#define ACE_BUSMODE_16BIT      0x0001
-
-#define ACE_STATUSL_CFGLOCK    0x0001
-#define ACE_STATUSL_MPULOCK    0x0002
-#define ACE_STATUSL_CFDETECT   0x0010
-#define ACE_STATUSL_DATARDY    0x0020
-#define ACE_STATUSL_DATAWRONLY 0x0040
-#define ACE_STATUSL_CFCMDRDY   0x0100
-
-#define ACE_SECCMD_RESET       0x0100
-#define ACE_SECCMD_IDENTIFY    0x0200
-#define ACE_SECCMD_READ                0x0300
-#define ACE_SECCMD_WRITE       0x0400
-#define ACE_SECCMD_ABORT       0x0600
-
-#define ACE_CTLL_LOCKREQ       0x0002
-#define ACE_CTLL_CFGRESET      0x0080
-
-#endif /* __HW_SYSTEMACE_H */
index 07388a7..5f52852 100644 (file)
@@ -1,7 +1,7 @@
 MMDIR=../..
 include $(MMDIR)/software/include.mak
 
-OBJECTS_ALL=divsi3.o libc.o crc16.o crc32.o console.o cfcard.o cffat.o system.o board.o irq.o
+OBJECTS_ALL=divsi3.o libc.o crc16.o crc32.o console.o fatfs.o system.o board.o irq.o
 OBJECTS=$(OBJECTS_ALL) softfloat.o softfloat-glue.o vsnprintf.o atof.o malloc.o uart-async.o
 OBJECTS_LIGHT=$(OBJECTS_ALL) vsnprintf-nofloat.o uart.o
 
@@ -31,18 +31,6 @@ board.o: ../../software/include/hw/sysctl.h
 board.o: ../../software/include/hw/common.h
 board.o: ../../software/include/base/stdlib.h
 board.o: ../../software/include/base/board.h
-cfcard.o: ../../software/include/hw/systemace.h
-cfcard.o: ../../software/include/hw/common.h
-cfcard.o: ../../software/include/base/cfcard.h
-cfcard.o: ../../software/include/base/console.h
-cffat.o: ../../software/include/base/stdlib.h
-cffat.o: ../../software/include/base/stdio.h
-cffat.o: ../../software/include/base/string.h
-cffat.o: ../../software/include/base/ctype.h
-cffat.o: ../../software/include/base/endian.h
-cffat.o: ../../software/include/base/cfcard.h
-cffat.o: ../../software/include/base/console.h
-cffat.o: ../../software/include/base/cffat.h
 console.o: ../../software/include/base/uart.h
 console.o: ../../software/include/base/console.h
 console.o: ../../software/include/base/stdio.h
@@ -50,6 +38,13 @@ console.o: ../../software/include/base/stdlib.h
 console.o: ../../software/include/base/stdarg.h
 crc16.o: ../../software/include/base/crc.h
 crc32.o: ../../software/include/base/crc.h
+fatfs.o: ../../software/include/base/stdlib.h
+fatfs.o: ../../software/include/base/stdio.h
+fatfs.o: ../../software/include/base/string.h
+fatfs.o: ../../software/include/base/ctype.h
+fatfs.o: ../../software/include/base/endian.h
+fatfs.o: ../../software/include/base/console.h
+fatfs.o: ../../software/include/base/fatfs.h
 libc.o: ../../software/include/base/ctype.h
 libc.o: ../../software/include/base/stdio.h
 libc.o: ../../software/include/base/stdlib.h
index aebc553..9445b24 100644 (file)
 #include <stdlib.h>
 #include <board.h>
 
-static const struct board_desc boards[3] = {
-       {
-               .id = 0x58343031, /* X401 */
-               .name = "Xilinx ML401 development board",
-               .clk_frequency = 100000000,
-               .sdram_size = 64,
-               .ddr_clkphase = 0,
-               .ddr_idelay = 0,
-               .ddr_dqsdelay = 244,
-               .memory_card = MEMCARD_SYSTEMACE,
-               .ethernet_phyadr = 0
-       },
+static const struct board_desc boards[1] = {
        {
                .id = 0x4D4F4E45, /* MONE */
                .name = "Milkymist One",
                .clk_frequency = 83333333,
-               .sdram_size = 64,
-               .ddr_clkphase = 0,
-               .ddr_idelay = 0,
-               .ddr_dqsdelay = 244,
-               .memory_card = MEMCARD_MICROSD,
+               .sdram_size = 128,
                .ethernet_phyadr = 1
        },
 };
diff --git a/software/libbase/cfcard.c b/software/libbase/cfcard.c
deleted file mode 100644 (file)
index 73f647a..0000000
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- * 
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- * 
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- * 
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <hw/systemace.h>
-#include <cfcard.h>
-#include <console.h>
-
-#define TIMEOUT 10000000
-
-int cf_init()
-{
-       int timeout;
-       
-       CSR_ACE_BUSMODE = ACE_BUSMODE_16BIT;
-       
-       if(!(CSR_ACE_STATUSL & ACE_STATUSL_CFDETECT)) return 0;
-       if((CSR_ACE_ERRORL != 0) || (CSR_ACE_ERRORH != 0)) return 0;
-       
-       CSR_ACE_CTLL |= ACE_CTLL_LOCKREQ;
-       timeout = TIMEOUT;
-       while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_MPULOCK))) timeout--;
-       if(timeout == 0) return 0;
-       
-       return 1;
-}
-
-int cf_readblock(unsigned int blocknr, unsigned char *buf)
-{
-       unsigned short int *bufw = (unsigned short int *)buf;
-       int buffer_count;
-       int i;
-       int timeout;
-       
-       /* See p. 39 */
-       timeout = TIMEOUT;
-       while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_CFCMDRDY))) timeout--;
-       if(timeout == 0) return 0;
-       
-       CSR_ACE_MLBAL = blocknr & 0x0000ffff;
-       CSR_ACE_MLBAH = (blocknr & 0x0fff0000) >> 16;
-       
-       CSR_ACE_SECCMD = ACE_SECCMD_READ|0x01;
-       
-       CSR_ACE_CTLL |= ACE_CTLL_CFGRESET;
-       
-       buffer_count = 16;
-       while(buffer_count > 0) {
-               timeout = TIMEOUT;
-               while((timeout > 0) && (!(CSR_ACE_STATUSL & ACE_STATUSL_DATARDY))) timeout--;
-               if(timeout == 0) return 0;
-
-               for(i=0;i<16;i++) {
-                       *bufw = CSR_ACE_DATA;
-                       /* SystemACE data buffer access seems little-endian. */
-                       *bufw = ((*bufw & 0xff00) >> 8) | ((*bufw & 0x00ff) << 8);
-                       bufw++;
-               }
-                       
-               buffer_count--;
-       }
-       
-       CSR_ACE_CTLL &= ~ACE_CTLL_CFGRESET;
-       
-       return 1;
-}
-
-void cf_done()
-{
-       CSR_ACE_CTLL &= ~ACE_CTLL_LOCKREQ;
-}
diff --git a/software/libbase/cffat.c b/software/libbase/cffat.c
deleted file mode 100644 (file)
index d12febf..0000000
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * Milkymist VJ SoC (Software)
- * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
- *
- * This program is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, version 3 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-
-#include <stdlib.h>
-#include <stdio.h>
-#include <string.h>
-#include <ctype.h>
-#include <endian.h>
-#include <cfcard.h>
-#include <console.h>
-#include <cffat.h>
-
-//#define DEBUG
-
-struct partition_descriptor {
-       unsigned char flags;
-       unsigned char start_head;
-       unsigned short start_cylinder;
-       unsigned char type;
-       unsigned char end_head;
-       unsigned short end_cylinder;
-       unsigned int start_sector;
-       unsigned int end_sector;
-} __attribute__((packed));
-
-struct firstsector {
-       unsigned char bootsector[446];
-       struct partition_descriptor partitions[4];
-       unsigned char signature[2];
-} __attribute__((packed));
-
-
-struct fat16_firstsector {
-       /* Common to FATxx */
-       char jmp[3];
-       char oem[8];
-       unsigned short bytes_per_sector;
-       unsigned char sectors_per_cluster;
-       unsigned short reserved_sectors;
-       unsigned char number_of_fat;
-       unsigned short max_root_entries;
-       unsigned short total_sectors_short;
-       unsigned char media_descriptor;
-       unsigned short sectors_per_fat;
-       unsigned short sectors_per_track;
-       unsigned short head_count;
-       unsigned int hidden_sectors;
-       unsigned int total_sectors;
-       
-       /* FAT16 specific */
-       unsigned char drive_nr;
-       unsigned char reserved;
-       unsigned char ext_boot_signature;
-       unsigned int id;
-       unsigned char volume_label[11];
-       unsigned char fstype[8];
-       unsigned char bootcode[448];
-       unsigned char signature[2];
-} __attribute__((packed));
-
-struct directory_entry {
-       unsigned char filename[8];
-       unsigned char extension[3];
-       unsigned char attributes;
-       unsigned char reserved;
-       unsigned char create_time_ms;
-       unsigned short create_time;
-       unsigned short create_date;
-       unsigned short last_access;
-       unsigned short ea_index;
-       unsigned short lastm_time;
-       unsigned short lastm_date;
-       unsigned short first_cluster;
-       unsigned int file_size;
-} __attribute__((packed));
-
-struct directory_entry_lfn {
-       unsigned char seq;
-       unsigned short name1[5]; /* UTF16 */
-       unsigned char attributes;
-       unsigned char reserved;
-       unsigned char checksum;
-       unsigned short name2[6];
-       unsigned short first_cluster;
-       unsigned short name3[2];
-} __attribute__((packed));
-
-#define PARTITION_TYPE_FAT16           0x06
-#define PARTITION_TYPE_FAT32           0x0b
-
-static int cffat_partition_start_sector;       /* Sector# of the beginning of the FAT16 partition */
-
-static int cffat_sectors_per_cluster;
-static int cffat_fat_sector;                   /* Sector of the first FAT */
-static int cffat_fat_entries;                  /* Number of entries in the FAT */
-static int cffat_max_root_entries;
-static int cffat_root_table_sector;            /* Sector# of the beginning of the root table */
-
-static int cffat_fat_cached_sector;
-static unsigned short int cffat_fat_sector_cache[CF_BLOCK_SIZE/2];
-
-static int cffat_dir_cached_sector;
-static struct directory_entry cffat_dir_sector_cache[CF_BLOCK_SIZE/sizeof(struct directory_entry)];
-
-static int cffat_data_start_sector;
-
-int cffat_init()
-{
-       struct firstsector s0;
-       struct fat16_firstsector s;
-       int i;
-
-       if(!cf_init()) {
-               printf("E: Unable to initialize CF card driver\n");
-               return 0;
-       }
-       
-       /* Read sector 0, with partition table */
-       if(!cf_readblock(0, (void *)&s0)) {
-               printf("E: Unable to read block 0\n");
-               return 0;
-       }
-
-       cffat_partition_start_sector = -1;
-       for(i=0;i<4;i++)
-               if((s0.partitions[i].type == PARTITION_TYPE_FAT16)
-                ||(s0.partitions[i].type == PARTITION_TYPE_FAT32)) {
-#ifdef DEBUG
-                       printf("I: Using partition #%d: start sector %08x, end sector %08x\n", i,
-                               le32toh(s0.partitions[i].start_sector), le32toh(s0.partitions[i].end_sector));
-#endif
-                       cffat_partition_start_sector = le32toh(s0.partitions[i].start_sector);
-                       break;
-               }
-       if(cffat_partition_start_sector == -1) {
-               printf("E: No FAT partition was found\n");
-               return 0;
-       }
-       
-       /* Read first FAT16 sector */
-       if(!cf_readblock(cffat_partition_start_sector, (void *)&s)) {
-               printf("E: Unable to read first FAT sector\n");
-               return 0;
-       }
-       
-#ifdef DEBUG
-       {
-               char oem[9];
-               char volume_label[12];
-               memcpy(oem, s.oem, 8);
-               oem[8] = 0;
-               memcpy(volume_label, s.volume_label, 11);
-               volume_label[11] = 0;
-               printf("I: OEM name: %s\n", oem);
-               printf("I: Volume label: %s\n", volume_label);
-       }
-#endif
-       
-       if(le16toh(s.bytes_per_sector) != CF_BLOCK_SIZE) {
-               printf("E: Unexpected number of bytes per sector\n");
-               return 0;
-       }
-       cffat_sectors_per_cluster = s.sectors_per_cluster;
-       
-       cffat_fat_entries = (le16toh(s.sectors_per_fat)*CF_BLOCK_SIZE)/2;
-       cffat_fat_sector = cffat_partition_start_sector + 1;
-       cffat_fat_cached_sector = -1;
-       
-       cffat_max_root_entries = le16toh(s.max_root_entries);
-       cffat_root_table_sector = cffat_fat_sector + s.number_of_fat*le16toh(s.sectors_per_fat);
-       cffat_dir_cached_sector = -1;
-       
-       cffat_data_start_sector = cffat_root_table_sector + (cffat_max_root_entries*sizeof(struct directory_entry))/CF_BLOCK_SIZE;
-
-       if(cffat_max_root_entries == 0) {
-               printf("E: Your memory card uses FAT32, which is not supported.\n");
-               printf("E: Please reformat your card using FAT16, e.g. use mkdosfs -F 16\n");
-               printf("E: FAT32 support would be an appreciated contribution.\n");
-               return 0;
-       }
-       
-#ifdef DEBUG
-       printf("I: Cluster is %d sectors, FAT has %d entries, FAT 1 is at sector %d,\nI: root table is at sector %d (max %d), data is at sector %d\n",
-               cffat_sectors_per_cluster, cffat_fat_entries, cffat_fat_sector,
-               cffat_root_table_sector, cffat_max_root_entries,
-               cffat_data_start_sector);
-#endif
-       return 1;
-}
-
-static int cffat_read_fat(int offset)
-{
-       int wanted_sector;
-       
-       if((offset < 0) || (offset >= cffat_fat_entries))
-               return -1;
-               
-       wanted_sector = cffat_fat_sector + (offset*2)/CF_BLOCK_SIZE;
-       if(wanted_sector != cffat_fat_cached_sector) {
-               if(!cf_readblock(wanted_sector, (void *)&cffat_fat_sector_cache)) {
-                       printf("E: CF failed (FAT), sector %d\n", wanted_sector);
-                       return -1;
-               }
-               cffat_fat_cached_sector = wanted_sector;
-       }
-       
-       return le16toh(cffat_fat_sector_cache[offset % (CF_BLOCK_SIZE/2)]);
-}
-
-static const struct directory_entry *cffat_read_root_directory(int offset)
-{
-       int wanted_sector;
-       
-       if((offset < 0) || (offset >= cffat_max_root_entries))
-               return NULL;
-
-       wanted_sector = cffat_root_table_sector + (offset*sizeof(struct directory_entry))/CF_BLOCK_SIZE;
-
-       if(wanted_sector != cffat_dir_cached_sector) {
-               if(!cf_readblock(wanted_sector, (void *)&cffat_dir_sector_cache)) {
-                       printf("E: CF failed (Rootdir), sector %d\n", wanted_sector);
-                       return NULL;
-               }
-               cffat_dir_cached_sector = wanted_sector;
-       }
-       return &cffat_dir_sector_cache[offset % (CF_BLOCK_SIZE/sizeof(struct directory_entry))];
-}
-
-static void lfn_to_ascii(const struct directory_entry_lfn *entry, char *name, int terminate)
-{
-       int i;
-       unsigned short c;
-
-       for(i=0;i<5;i++) {
-               c = le16toh(entry->name1[i]);
-               if(c <= 255) {
-                       *name = c;
-                       name++;
-                       if(c == 0) return;
-               }
-       }
-       for(i=0;i<6;i++) {
-               c = le16toh(entry->name2[i]);
-               if(c <= 255) {
-                       *name = c;
-                       name++;
-                       if(c == 0) return;
-               }
-       }
-       for(i=0;i<2;i++) {
-               c = le16toh(entry->name3[i]);
-               if(c <= 255) {
-                       *name = c;
-                       name++;
-                       if(c == 0) return;
-               }
-       }
-
-       if(terminate)
-               *name = 0;
-}
-
-static int cffat_is_regular(const struct directory_entry *entry)
-{
-       return ((entry->attributes & 0x10) == 0)
-               && ((entry->attributes & 0x08) == 0)
-               && (entry->filename[0] != 0xe5);
-}
-
-int cffat_list_files(cffat_dir_callback cb, void *param)
-{
-       const struct directory_entry *entry;
-       char fmtbuf[8+1+3+1];
-       char longname[131];
-       int has_longname;
-       int i, j, k;
-
-       has_longname = 0;
-       longname[sizeof(longname)-1] = 0; /* avoid crashing when reading a corrupt FS */
-       for(k=0;k<cffat_max_root_entries;k++) {
-               entry = cffat_read_root_directory(k);
-#ifdef DEBUG
-               printf("I: Read entry with attribute %02x\n", entry->attributes);
-#endif
-               if(entry->attributes == 0x0f) {
-                       const struct directory_entry_lfn *entry_lfn;
-                       unsigned char frag;
-                       int terminate;
-
-                       entry_lfn = (const struct directory_entry_lfn *)entry;
-                       frag = entry_lfn->seq & 0x3f;
-                       terminate = entry_lfn->seq & 0x40;
-                       if(frag*13 < sizeof(longname)) {
-                               lfn_to_ascii((const struct directory_entry_lfn *)entry, &longname[(frag-1)*13], terminate);
-                               if(frag == 1) has_longname = 1;
-                       }
-                       continue;
-               } else {
-                       if(!cffat_is_regular(entry)) {
-                               has_longname = 0;
-                               continue;
-                       }
-               }
-               if(entry == NULL) return 0;
-               if(entry->filename[0] == 0) {
-                       has_longname = 0;
-                       break;
-               }
-               j = 0;
-               for(i=0;i<8;i++) {
-                       if(entry->filename[i] == ' ') break;
-                       fmtbuf[j++] = entry->filename[i];
-               }
-               fmtbuf[j++] = '.';
-               for(i=0;i<3;i++) {
-                       if(entry->extension[i] == ' ') break;
-                       fmtbuf[j++] = entry->extension[i];
-               }
-               fmtbuf[j++] = 0;
-               if(!cb(fmtbuf, has_longname ? longname : fmtbuf, param)) return 0;
-               has_longname = 0;
-       }
-       return 1;
-}
-
-static const struct directory_entry *cffat_find_file_by_name(const char *filename)
-{
-       char searched_filename[8];
-       char searched_extension[3];
-       char *dot;
-       const char *c;
-       int i;
-       const struct directory_entry *entry;
-       
-       dot = strrchr(filename, '.');
-       if(dot == NULL)
-               return NULL;
-       
-       memset(searched_filename, ' ', 8);
-       memset(searched_extension, ' ', 3);
-       i = 0;
-       for(c=filename;c<dot;c++)
-               searched_filename[i++] = toupper(*c);
-               
-       i = 0;
-       for(c=dot+1;*c!=0;c++)
-               searched_extension[i++] = toupper(*c);
-               
-       for(i=0;i<cffat_max_root_entries;i++) {
-               entry = cffat_read_root_directory(i);
-               if(entry == NULL) break;
-               if(entry->filename[0] == 0) break;
-               if(!cffat_is_regular(entry)) continue;
-               if(!memcmp(searched_filename, entry->filename, 8)
-                &&!memcmp(searched_extension, entry->extension, 3))
-                       return entry;
-       }
-       return NULL;
-}
-
-static int cffat_load_cluster(int clustern, char *buffer, int maxsectors)
-{
-       int startsector;
-       int i;
-       int toread;
-       
-       clustern = clustern - 2;
-       startsector = cffat_data_start_sector + clustern*cffat_sectors_per_cluster;
-       if(maxsectors < cffat_sectors_per_cluster)
-               toread = maxsectors;
-       else
-               toread = cffat_sectors_per_cluster;
-       for(i=0;i<toread;i++)
-               if(!cf_readblock(startsector+i, (unsigned char *)buffer+i*CF_BLOCK_SIZE)) {
-                       printf("E: CF failed (Cluster), sector %d\n", startsector+i);
-                       return 0;
-               }
-       return 1;
-}
-
-int cffat_load(const char *filename, char *buffer, int size, int *realsize)
-{
-       const struct directory_entry *entry;
-       int cluster_size;
-       int cluster;
-       int n;
-       
-       cluster_size = cffat_sectors_per_cluster*CF_BLOCK_SIZE;
-       size /= CF_BLOCK_SIZE;
-       
-       entry = cffat_find_file_by_name(filename);
-       if(entry == NULL) {
-               printf("E: File not found: %s\n", filename);
-               return 0;
-       }
-       
-       if(realsize != NULL) *realsize = le32toh(entry->file_size);
-       
-       n = 0;
-       cluster = le16toh(entry->first_cluster);
-       while(size > 0) {
-               if(!cffat_load_cluster(cluster, buffer+n*cluster_size, size))
-                       return 0;
-               size -= cffat_sectors_per_cluster;
-               n++;
-               cluster = cffat_read_fat(cluster);
-               if(cluster >= 0xFFF8) break;
-               if(cluster == -1) return 0;
-       }
-       //putsnonl("\n");
-       
-       return n*cluster_size;
-}
-
-void cffat_done()
-{
-       cf_done();
-}
diff --git a/software/libbase/fatfs.c b/software/libbase/fatfs.c
new file mode 100644 (file)
index 0000000..c01b70c
--- /dev/null
@@ -0,0 +1,433 @@
+/*
+ * Milkymist VJ SoC (Software)
+ * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, version 3 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <stdlib.h>
+#include <stdio.h>
+#include <string.h>
+#include <ctype.h>
+#include <endian.h>
+#include <console.h>
+#include <fatfs.h>
+
+//#define DEBUG
+
+#define BLOCK_SIZE 512
+
+struct partition_descriptor {
+       unsigned char flags;
+       unsigned char start_head;
+       unsigned short start_cylinder;
+       unsigned char type;
+       unsigned char end_head;
+       unsigned short end_cylinder;
+       unsigned int start_sector;
+       unsigned int end_sector;
+} __attribute__((packed));
+
+struct firstsector {
+       unsigned char bootsector[446];
+       struct partition_descriptor partitions[4];
+       unsigned char signature[2];
+} __attribute__((packed));
+
+
+struct fat16_firstsector {
+       /* Common to FATxx */
+       char jmp[3];
+       char oem[8];
+       unsigned short bytes_per_sector;
+       unsigned char sectors_per_cluster;
+       unsigned short reserved_sectors;
+       unsigned char number_of_fat;
+       unsigned short max_root_entries;
+       unsigned short total_sectors_short;
+       unsigned char media_descriptor;
+       unsigned short sectors_per_fat;
+       unsigned short sectors_per_track;
+       unsigned short head_count;
+       unsigned int hidden_sectors;
+       unsigned int total_sectors;
+       
+       /* FAT16 specific */
+       unsigned char drive_nr;
+       unsigned char reserved;
+       unsigned char ext_boot_signature;
+       unsigned int id;
+       unsigned char volume_label[11];
+       unsigned char fstype[8];
+       unsigned char bootcode[448];
+       unsigned char signature[2];
+} __attribute__((packed));
+
+struct directory_entry {
+       unsigned char filename[8];
+       unsigned char extension[3];
+       unsigned char attributes;
+       unsigned char reserved;
+       unsigned char create_time_ms;
+       unsigned short create_time;
+       unsigned short create_date;
+       unsigned short last_access;
+       unsigned short ea_index;
+       unsigned short lastm_time;
+       unsigned short lastm_date;
+       unsigned short first_cluster;
+       unsigned int file_size;
+} __attribute__((packed));
+
+struct directory_entry_lfn {
+       unsigned char seq;
+       unsigned short name1[5]; /* UTF16 */
+       unsigned char attributes;
+       unsigned char reserved;
+       unsigned char checksum;
+       unsigned short name2[6];
+       unsigned short first_cluster;
+       unsigned short name3[2];
+} __attribute__((packed));
+
+#define PARTITION_TYPE_FAT16           0x06
+#define PARTITION_TYPE_FAT32           0x0b
+
+static int fatfs_partition_start_sector;       /* Sector# of the beginning of the FAT16 partition */
+
+static int fatfs_sectors_per_cluster;
+static int fatfs_fat_sector;                   /* Sector of the first FAT */
+static int fatfs_fat_entries;                  /* Number of entries in the FAT */
+static int fatfs_max_root_entries;
+static int fatfs_root_table_sector;            /* Sector# of the beginning of the root table */
+
+static int fatfs_fat_cached_sector;
+static unsigned short int fatfs_fat_sector_cache[BLOCK_SIZE/2];
+
+static int fatfs_dir_cached_sector;
+static struct directory_entry fatfs_dir_sector_cache[BLOCK_SIZE/sizeof(struct directory_entry)];
+
+static int fatfs_data_start_sector;
+
+int fatfs_init()
+{
+       struct firstsector s0;
+       struct fat16_firstsector s;
+       int i;
+
+       if(/* !cf_init() */ 1) {
+               printf("E: Unable to initialize memory card driver\n");
+               return 0;
+       }
+       
+       /* Read sector 0, with partition table */
+       if(/* !cf_readblock(0, (void *)&s0) */ 1) {
+               printf("E: Unable to read block 0\n");
+               return 0;
+       }
+
+       fatfs_partition_start_sector = -1;
+       for(i=0;i<4;i++)
+               if((s0.partitions[i].type == PARTITION_TYPE_FAT16)
+                ||(s0.partitions[i].type == PARTITION_TYPE_FAT32)) {
+#ifdef DEBUG
+                       printf("I: Using partition #%d: start sector %08x, end sector %08x\n", i,
+                               le32toh(s0.partitions[i].start_sector), le32toh(s0.partitions[i].end_sector));
+#endif
+                       fatfs_partition_start_sector = le32toh(s0.partitions[i].start_sector);
+                       break;
+               }
+       if(fatfs_partition_start_sector == -1) {
+               printf("E: No FAT partition was found\n");
+               return 0;
+       }
+       
+       /* Read first FAT16 sector */
+       if(/* !cf_readblock(fatfs_partition_start_sector, (void *)&s) */ 1) {
+               printf("E: Unable to read first FAT sector\n");
+               return 0;
+       }
+       
+#ifdef DEBUG
+       {
+               char oem[9];
+               char volume_label[12];
+               memcpy(oem, s.oem, 8);
+               oem[8] = 0;
+               memcpy(volume_label, s.volume_label, 11);
+               volume_label[11] = 0;
+               printf("I: OEM name: %s\n", oem);
+               printf("I: Volume label: %s\n", volume_label);
+       }
+#endif
+       
+       if(le16toh(s.bytes_per_sector) != BLOCK_SIZE) {
+               printf("E: Unexpected number of bytes per sector\n");
+               return 0;
+       }
+       fatfs_sectors_per_cluster = s.sectors_per_cluster;
+       
+       fatfs_fat_entries = (le16toh(s.sectors_per_fat)*BLOCK_SIZE)/2;
+       fatfs_fat_sector = fatfs_partition_start_sector + 1;
+       fatfs_fat_cached_sector = -1;
+       
+       fatfs_max_root_entries = le16toh(s.max_root_entries);
+       fatfs_root_table_sector = fatfs_fat_sector + s.number_of_fat*le16toh(s.sectors_per_fat);
+       fatfs_dir_cached_sector = -1;
+       
+       fatfs_data_start_sector = fatfs_root_table_sector + (fatfs_max_root_entries*sizeof(struct directory_entry))/BLOCK_SIZE;
+
+       if(fatfs_max_root_entries == 0) {
+               printf("E: Your memory card uses FAT32, which is not supported.\n");
+               printf("E: Please reformat your card using FAT16, e.g. use mkdosfs -F 16\n");
+               printf("E: FAT32 support would be an appreciated contribution.\n");
+               return 0;
+       }
+       
+#ifdef DEBUG
+       printf("I: Cluster is %d sectors, FAT has %d entries, FAT 1 is at sector %d,\nI: root table is at sector %d (max %d), data is at sector %d\n",
+               fatfs_sectors_per_cluster, fatfs_fat_entries, fatfs_fat_sector,
+               fatfs_root_table_sector, fatfs_max_root_entries,
+               fatfs_data_start_sector);
+#endif
+       return 1;
+}
+
+static int fatfs_read_fat(int offset)
+{
+       int wanted_sector;
+       
+       if((offset < 0) || (offset >= fatfs_fat_entries))
+               return -1;
+               
+       wanted_sector = fatfs_fat_sector + (offset*2)/BLOCK_SIZE;
+       if(wanted_sector != fatfs_fat_cached_sector) {
+               if(/* !cf_readblock(wanted_sector, (void *)&fatfs_fat_sector_cache) */ 1) {
+                       printf("E: Memory card failed (FAT), sector %d\n", wanted_sector);
+                       return -1;
+               }
+               fatfs_fat_cached_sector = wanted_sector;
+       }
+       
+       return le16toh(fatfs_fat_sector_cache[offset % (BLOCK_SIZE/2)]);
+}
+
+static const struct directory_entry *fatfs_read_root_directory(int offset)
+{
+       int wanted_sector;
+       
+       if((offset < 0) || (offset >= fatfs_max_root_entries))
+               return NULL;
+
+       wanted_sector = fatfs_root_table_sector + (offset*sizeof(struct directory_entry))/BLOCK_SIZE;
+
+       if(wanted_sector != fatfs_dir_cached_sector) {
+               if(/* !cf_readblock(wanted_sector, (void *)&fatfs_dir_sector_cache) */ 1) {
+                       printf("E: Memory card failed (Rootdir), sector %d\n", wanted_sector);
+                       return NULL;
+               }
+               fatfs_dir_cached_sector = wanted_sector;
+       }
+       return &fatfs_dir_sector_cache[offset % (BLOCK_SIZE/sizeof(struct directory_entry))];
+}
+
+static void lfn_to_ascii(const struct directory_entry_lfn *entry, char *name, int terminate)
+{
+       int i;
+       unsigned short c;
+
+       for(i=0;i<5;i++) {
+               c = le16toh(entry->name1[i]);
+               if(c <= 255) {
+                       *name = c;
+                       name++;
+                       if(c == 0) return;
+               }
+       }
+       for(i=0;i<6;i++) {
+               c = le16toh(entry->name2[i]);
+               if(c <= 255) {
+                       *name = c;
+                       name++;
+                       if(c == 0) return;
+               }
+       }
+       for(i=0;i<2;i++) {
+               c = le16toh(entry->name3[i]);
+               if(c <= 255) {
+                       *name = c;
+                       name++;
+                       if(c == 0) return;
+               }
+       }
+
+       if(terminate)
+               *name = 0;
+}
+
+static int fatfs_is_regular(const struct directory_entry *entry)
+{
+       return ((entry->attributes & 0x10) == 0)
+               && ((entry->attributes & 0x08) == 0)
+               && (entry->filename[0] != 0xe5);
+}
+
+int fatfs_list_files(fatfs_dir_callback cb, void *param)
+{
+       const struct directory_entry *entry;
+       char fmtbuf[8+1+3+1];
+       char longname[131];
+       int has_longname;
+       int i, j, k;
+
+       has_longname = 0;
+       longname[sizeof(longname)-1] = 0; /* avoid crashing when reading a corrupt FS */
+       for(k=0;k<fatfs_max_root_entries;k++) {
+               entry = fatfs_read_root_directory(k);
+#ifdef DEBUG
+               printf("I: Read entry with attribute %02x\n", entry->attributes);
+#endif
+               if(entry->attributes == 0x0f) {
+                       const struct directory_entry_lfn *entry_lfn;
+                       unsigned char frag;
+                       int terminate;
+
+                       entry_lfn = (const struct directory_entry_lfn *)entry;
+                       frag = entry_lfn->seq & 0x3f;
+                       terminate = entry_lfn->seq & 0x40;
+                       if(frag*13 < sizeof(longname)) {
+                               lfn_to_ascii((const struct directory_entry_lfn *)entry, &longname[(frag-1)*13], terminate);
+                               if(frag == 1) has_longname = 1;
+                       }
+                       continue;
+               } else {
+                       if(!fatfs_is_regular(entry)) {
+                               has_longname = 0;
+                               continue;
+                       }
+               }
+               if(entry == NULL) return 0;
+               if(entry->filename[0] == 0) {
+                       has_longname = 0;
+                       break;
+               }
+               j = 0;
+               for(i=0;i<8;i++) {
+                       if(entry->filename[i] == ' ') break;
+                       fmtbuf[j++] = entry->filename[i];
+               }
+               fmtbuf[j++] = '.';
+               for(i=0;i<3;i++) {
+                       if(entry->extension[i] == ' ') break;
+                       fmtbuf[j++] = entry->extension[i];
+               }
+               fmtbuf[j++] = 0;
+               if(!cb(fmtbuf, has_longname ? longname : fmtbuf, param)) return 0;
+               has_longname = 0;
+       }
+       return 1;
+}
+
+static const struct directory_entry *fatfs_find_file_by_name(const char *filename)
+{
+       char searched_filename[8];
+       char searched_extension[3];
+       char *dot;
+       const char *c;
+       int i;
+       const struct directory_entry *entry;
+       
+       dot = strrchr(filename, '.');
+       if(dot == NULL)
+               return NULL;
+       
+       memset(searched_filename, ' ', 8);
+       memset(searched_extension, ' ', 3);
+       i = 0;
+       for(c=filename;c<dot;c++)
+               searched_filename[i++] = toupper(*c);
+               
+       i = 0;
+       for(c=dot+1;*c!=0;c++)
+               searched_extension[i++] = toupper(*c);
+               
+       for(i=0;i<fatfs_max_root_entries;i++) {
+               entry = fatfs_read_root_directory(i);
+               if(entry == NULL) break;
+               if(entry->filename[0] == 0) break;
+               if(!fatfs_is_regular(entry)) continue;
+               if(!memcmp(searched_filename, entry->filename, 8)
+                &&!memcmp(searched_extension, entry->extension, 3))
+                       return entry;
+       }
+       return NULL;
+}
+
+static int fatfs_load_cluster(int clustern, char *buffer, int maxsectors)
+{
+       int startsector;
+       int i;
+       int toread;
+       
+       clustern = clustern - 2;
+       startsector = fatfs_data_start_sector + clustern*fatfs_sectors_per_cluster;
+       if(maxsectors < fatfs_sectors_per_cluster)
+               toread = maxsectors;
+       else
+               toread = fatfs_sectors_per_cluster;
+       for(i=0;i<toread;i++)
+               if(/* !cf_readblock(startsector+i, (unsigned char *)buffer+i*CF_BLOCK_SIZE) */ 1) {
+                       printf("E: Memory card failed (Cluster), sector %d\n", startsector+i);
+                       return 0;
+               }
+       return 1;
+}
+
+int fatfs_load(const char *filename, char *buffer, int size, int *realsize)
+{
+       const struct directory_entry *entry;
+       int cluster_size;
+       int cluster;
+       int n;
+       
+       cluster_size = fatfs_sectors_per_cluster*BLOCK_SIZE;
+       size /= BLOCK_SIZE;
+       
+       entry = fatfs_find_file_by_name(filename);
+       if(entry == NULL) {
+               printf("E: File not found: %s\n", filename);
+               return 0;
+       }
+       
+       if(realsize != NULL) *realsize = le32toh(entry->file_size);
+       
+       n = 0;
+       cluster = le16toh(entry->first_cluster);
+       while(size > 0) {
+               if(!fatfs_load_cluster(cluster, buffer+n*cluster_size, size))
+                       return 0;
+               size -= fatfs_sectors_per_cluster;
+               n++;
+               cluster = fatfs_read_fat(cluster);
+               if(cluster >= 0xFFF8) break;
+               if(cluster == -1) return 0;
+       }
+       //putsnonl("\n");
+       
+       return n*cluster_size;
+}
+
+void fatfs_done()
+{
+       /* cf_done(); */
+}
index 42cf1bf..8ae8552 100644 (file)
@@ -95,11 +95,11 @@ send_init_return:
        PRINT(seqcomplete)
 
 #ifdef FEAT_PBC_MANUAL_CALIBRATION
-       /* if PBC is pushed, go into debug/manual mode */
+       /* if BTN3 is pushed, go into debug/manual mode */
        mvhi    r1, hi(CSR_GPIO_IN)
        ori     r1, r1, lo(CSR_GPIO_IN)
        lw      r2, (r1+0)
-       andi    r2, r2, (GPIO_PBC)
+       andi    r2, r2, (GPIO_BTN3)
        bne     r2, r0, mancal
 #endif