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[mw/milkymist.git] / cores / norflash16 / rtl / norflash16.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 module norflash16 #(
19         parameter adr_width = 22,
20         parameter timing = 4'd12
21 ) (
22         input sys_clk,
23         input sys_rst,
24
25         input [31:0] wb_adr_i,
26         output reg [31:0] wb_dat_o,
27         input wb_stb_i,
28         input wb_cyc_i,
29         output reg wb_ack_o,
30         
31         output [adr_width-1:0] flash_adr,
32         input [15:0] flash_d
33 );
34
35 reg [adr_width-1-1:0] flash_adr_msb;
36 reg flash_adr_lsb;
37
38 assign flash_adr = {flash_adr_msb, flash_adr_lsb};
39
40 reg load;
41 always @(posedge sys_clk) begin
42         /* Use IOB registers to prevent glitches on address lines */
43         if(wb_cyc_i & wb_stb_i) /* register only when needed to reduce EMI */
44                 flash_adr_msb <= wb_adr_i[adr_width-1:2];
45         if(load) begin
46                 case(flash_adr_lsb)
47                         1'b0: wb_dat_o[31:16] <= {flash_d[7:0], flash_d[15:8]};
48                         1'b1: wb_dat_o[15:0] <= {flash_d[7:0], flash_d[15:8]};
49                 endcase
50                 flash_adr_lsb <= ~flash_adr_lsb;
51         end
52         if(sys_rst)
53                 flash_adr_lsb <= 1'b0;
54 end
55
56 /*
57  * Timing of the flash chips is typically 110ns.
58  */
59 reg [3:0] counter;
60 reg counter_en;
61 wire counter_done = (counter == timing);
62 always @(posedge sys_clk) begin
63         if(sys_rst)
64                 counter <= 4'd0;
65         else begin
66                 if(counter_en & ~counter_done)
67                         counter <= counter + 4'd1;
68                 else
69                         counter <= 4'd0;
70         end
71 end
72
73 reg [1:0] state;
74 reg [1:0] next_state;
75 always @(posedge sys_clk) begin
76         if(sys_rst)
77                 state <= 1'b0;
78         else
79                 state <= next_state;
80 end
81
82 always @(*) begin
83         next_state = state;
84         counter_en = 1'b0;
85         load = 1'b0;
86         wb_ack_o = 1'b0;
87
88         case(state)
89                 2'd0: begin
90                         if(wb_cyc_i & wb_stb_i)
91                                 next_state = 2'd1;
92                 end
93
94                 2'd1: begin
95                         counter_en = 1'b1;
96                         if(counter_done) begin
97                                 load = 1'b1;
98                                 if(flash_adr_lsb)
99                                         next_state = 2'd2;
100                         end
101                 end
102
103                 2'd2: begin
104                         wb_ack_o = 1'b1;
105                         next_state = 2'd0;
106                 end
107         endcase
108 end
109
110 endmodule