Fixed timing problem
[mw/milkymist.git] / boards / xilinx-ml401 / synthesis / precision.tcl
1 new_project -name "milkymist" -folder "." -createimpl_name "milkymist_impl"
2
3 setup_design -manufacturer "Xilinx" -family "VIRTEX-4" -part "4VLX25FF668" -speed "10"
4 setup_design -retiming
5 setup_design -max_fanout=10000
6 setup_design -design "system"
7 setup_design -basename "system"
8
9 setup_design -compile_for_area=false
10 setup_design -compile_for_timing=true
11
12 source "loadsources.tcl"
13 add_input_file "system.ucf" -exclude="false"
14 add_input_file "../ioffs.sdc"
15
16 compile
17 synthesize
18
19 save_impl
20 close_project