ab9f8e4c3305678e1272663c0871d4e955a7ec5d
[mw/milkymist.git] / boards / milkymist-one / rtl / vga.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module vga #(
21         parameter csr_addr = 4'h0,
22         parameter fml_depth = 26
23 ) (
24         input sys_clk,
25         input sys_rst,
26         
27         /* Configuration interface */
28         input [13:0] csr_a,
29         input csr_we,
30         input [31:0] csr_di,
31         output [31:0] csr_do,
32         
33         /* Framebuffer FML 4x64 interface */
34         output [fml_depth-1:0] fml_adr,
35         output fml_stb,
36         input fml_ack,
37         input [63:0] fml_di,
38         
39         /* VGA pads */
40         output vga_psave_n,
41         output vga_hsync_n,
42         output vga_vsync_n,
43         output vga_sync_n,
44         output vga_blank_n,
45         output [7:0] vga_r,
46         output [7:0] vga_g,
47         output [7:0] vga_b,
48         output vga_clkout
49 );
50
51 wire vga_clk_dcm;
52 wire vga_clk_n_dcm;
53 wire vga_clk;
54 wire vga_clk_n;
55
56 DCM_SP #(
57         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
58
59         .CLKFX_DIVIDE(8),               // 1 to 32
60         .CLKFX_MULTIPLY(2),             // 2 to 32
61
62         .CLKIN_DIVIDE_BY_2("FALSE"),
63         .CLKIN_PERIOD(`CLOCK_PERIOD),
64         .CLKOUT_PHASE_SHIFT("VARIABLE"),
65         .CLK_FEEDBACK("1X"),
66         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
67         .DFS_FREQUENCY_MODE("LOW"),
68         .DLL_FREQUENCY_MODE("LOW"),
69         .DUTY_CYCLE_CORRECTION("TRUE"),
70         .PHASE_SHIFT(0),
71         .STARTUP_WAIT("FALSE")
72 ) clkgen_dqs (
73         .CLK0(),
74         .CLK90(),
75         .CLK180(),
76         .CLK270(),
77
78         .CLK2X(),
79         .CLK2X180(),
80
81         .CLKDV(),
82         .CLKFX(vga_clk_dcm),
83         .CLKFX180(vga_clk_n_dcm),
84         .LOCKED(),
85         .CLKFB(vga_clk),
86         .CLKIN(sys_clk),
87         .RST(sys_rst),
88
89         .PSEN(1'b0)
90 );
91 AUTOBUF b_p(
92         .I(vga_clk_dcm),
93         .O(vga_clk)
94 );
95 AUTOBUF b_n(
96         .I(vga_clk_n_dcm),
97         .O(vga_clk_n)
98 );
99
100 ODDR2 #(
101         .DDR_ALIGNMENT("NONE"),
102         .INIT(1'b0),
103         .SRTYPE("SYNC")
104 ) clock_forward (
105         .Q(vga_clkout),
106         .C0(vga_clk),
107         .C1(vga_clk_n),
108         .CE(1'b1),
109         .D0(1'b1),
110         .D1(1'b0),
111         .R(1'b0),
112         .S(1'b0)
113 );
114
115 vgafb #(
116         .csr_addr(csr_addr),
117         .fml_depth(fml_depth)
118 ) vgafb (
119         .sys_clk(sys_clk),
120         .sys_rst(sys_rst),
121         
122         .csr_a(csr_a),
123         .csr_we(csr_we),
124         .csr_di(csr_di),
125         .csr_do(csr_do),
126         
127         .fml_adr(fml_adr),
128         .fml_stb(fml_stb),
129         .fml_ack(fml_ack),
130         .fml_di(fml_di),
131         
132         .vga_clk(vga_clk),
133         .vga_psave_n(vga_psave_n),
134         .vga_hsync_n(vga_hsync_n),
135         .vga_vsync_n(vga_vsync_n),
136         .vga_sync_n(vga_sync_n),
137         .vga_blank_n(vga_blank_n),
138         .vga_r(vga_r),
139         .vga_g(vga_g),
140         .vga_b(vga_b)
141 );
142
143 endmodule