443bc282e3f88021b169c0094d1c48d7efdf1095
[mw/milkymist.git] / boards / milkymist-one / rtl / vga.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module vga #(
21         parameter csr_addr = 4'h0,
22         parameter fml_depth = 26
23 ) (
24         input sys_clk,
25         input sys_rst,
26         
27         /* Configuration interface */
28         input [13:0] csr_a,
29         input csr_we,
30         input [31:0] csr_di,
31         output [31:0] csr_do,
32         
33         /* Framebuffer FML 4x64 interface */
34         output [fml_depth-1:0] fml_adr,
35         output fml_stb,
36         input fml_ack,
37         input [63:0] fml_di,
38         
39         /* VGA pads */
40         output vga_psave_n,
41         output vga_hsync_n,
42         output vga_vsync_n,
43         output [7:0] vga_r,
44         output [7:0] vga_g,
45         output [7:0] vga_b,
46         output vga_clk
47 );
48
49 wire vga_iclk_dcm;
50 wire vga_iclk_n_dcm;
51 wire vga_iclk;
52 wire vga_iclk_n;
53
54 DCM_SP #(
55         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
56
57         .CLKFX_DIVIDE(10),              // 1 to 32
58         .CLKFX_MULTIPLY(3),             // 2 to 32
59
60         .CLKIN_DIVIDE_BY_2("FALSE"),
61         .CLKIN_PERIOD(`CLOCK_PERIOD),
62         .CLKOUT_PHASE_SHIFT("NONE"),
63         .CLK_FEEDBACK("1X"),
64         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
65         .DFS_FREQUENCY_MODE("LOW"),
66         .DLL_FREQUENCY_MODE("LOW"),
67         .DUTY_CYCLE_CORRECTION("TRUE"),
68         .PHASE_SHIFT(0),
69         .STARTUP_WAIT("FALSE")
70 ) clkgen_vga (
71         .CLK0(),
72         .CLK90(),
73         .CLK180(),
74         .CLK270(),
75
76         .CLK2X(),
77         .CLK2X180(),
78
79         .CLKDV(),
80         .CLKFX(vga_iclk_dcm),
81         .CLKFX180(vga_iclk_n_dcm),
82         .LOCKED(),
83         .CLKFB(vga_iclk),
84         .CLKIN(sys_clk),
85         .RST(sys_rst),
86
87         .PSEN(1'b0)
88 );
89 AUTOBUF b_p(
90         .I(vga_iclk_dcm),
91         .O(vga_iclk)
92 );
93 AUTOBUF b_n(
94         .I(vga_iclk_n_dcm),
95         .O(vga_iclk_n)
96 );
97
98 ODDR2 #(
99         .DDR_ALIGNMENT("NONE"),
100         .INIT(1'b0),
101         .SRTYPE("SYNC")
102 ) clock_forward (
103         .Q(vga_clk),
104         .C0(vga_iclk),
105         .C1(vga_iclk_n),
106         .CE(1'b1),
107         .D0(1'b1),
108         .D1(1'b0),
109         .R(1'b0),
110         .S(1'b0)
111 );
112
113 vgafb #(
114         .csr_addr(csr_addr),
115         .fml_depth(fml_depth)
116 ) vgafb (
117         .sys_clk(sys_clk),
118         .sys_rst(sys_rst),
119         
120         .csr_a(csr_a),
121         .csr_we(csr_we),
122         .csr_di(csr_di),
123         .csr_do(csr_do),
124         
125         .fml_adr(fml_adr),
126         .fml_stb(fml_stb),
127         .fml_ack(fml_ack),
128         .fml_di(fml_di),
129         
130         .vga_clk(vga_iclk),
131         .vga_psave_n(vga_psave_n),
132         .vga_hsync_n(vga_hsync_n),
133         .vga_vsync_n(vga_vsync_n),
134         .vga_r(vga_r),
135         .vga_g(vga_g),
136         .vga_b(vga_b)
137 );
138
139 endmodule