Removed ML401 support
[mw/milkymist.git] / boards / milkymist-one / rtl / system.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module system(
21         input clk50,
22         
23         // Boot ROM
24         output [23:0] flash_adr,
25         input [15:0] flash_d,
26         output flash_oe_n,
27         output flash_we_n,
28         output flash_ce_n,
29         output flash_rst_n,
30         input flash_sts,
31
32         // UART
33         input uart_rx,
34         output uart_tx,
35
36         // GPIO
37         input btn1,
38         input btn2,
39         input btn3,
40         output led1,
41         output led2,
42
43         // DDR SDRAM
44         output sdram_clk_p,
45         output sdram_clk_n,
46         output sdram_cke,
47         output sdram_cs_n,
48         output sdram_we_n,
49         output sdram_cas_n,
50         output sdram_ras_n,
51         output [3:0] sdram_dm,
52         output [12:0] sdram_adr,
53         output [1:0] sdram_ba,
54         inout [31:0] sdram_dq,
55         inout [3:0] sdram_dqs,
56
57         // VGA
58         output vga_psave_n,
59         output vga_hsync_n,
60         output vga_vsync_n,
61         output [7:0] vga_r,
62         output [7:0] vga_g,
63         output [7:0] vga_b,
64         output vga_clk,
65         inout vga_sda,
66         output vga_sdc,
67
68         // Memory card
69         inout [3:0] mc_d,
70         inout mc_cmd,
71         output mc_clk,
72         
73         // AC97
74         input ac97_clk,
75         input ac97_sin,
76         output ac97_sout,
77         output ac97_sync,
78         output ac97_rst_n,
79
80         // USB
81         output usba_spd,
82         output usba_oe_n,
83         input usba_rcv,
84         inout usba_vp,
85         inout usba_vm,
86
87         output usbb_spd,
88         output usbb_oe_n,
89         input usbb_rcv,
90         inout usbb_vp,
91         inout usbb_vm,
92
93         // Ethernet
94         output phy_rst_n,
95         input phy_tx_clk,
96         output [3:0] phy_tx_data,
97         output phy_tx_en,
98         output phy_tx_er,
99         input phy_rx_clk,
100         input [3:0] phy_rx_data,
101         input phy_dv,
102         input phy_rx_er,
103         input phy_col,
104         input phy_crs,
105         input phy_irq_n,
106         output phy_mii_clk,
107         inout phy_mii_data,
108         output reg phy_clk,
109
110         // Video Input
111         input [7:0] videoin_p,
112         input videoin_hs,
113         input videoin_vs,
114         input videoin_field,
115         input videoin_llc,
116         input videoin_irq_n,
117         input videoin_rst_n,
118         inout videoin_sda,
119         output videoin_sdc,
120
121         // MIDI
122         output midi_tx,
123         input midi_rx,
124
125         // DMX512
126         input dmxa_r,
127         output dmxa_de,
128         output dmxa_d,
129         input dmxb_r,
130         output dmxb_de,
131         output dmxb_d,
132
133         // IR
134         input ir_rx,
135
136         // Expansion connector
137         input [11:0] exp
138 );
139
140 //------------------------------------------------------------------
141 // Clock and Reset Generation
142 //------------------------------------------------------------------
143 wire sys_clk;
144 wire sys_clk_n;
145 wire hard_reset;
146
147 `ifndef SIMULATION
148 wire sys_clk_dcm;
149 wire sys_clk_n_dcm;
150
151 DCM_SP #(
152         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
153
154         .CLKFX_DIVIDE(3),               // 1 to 32
155         .CLKFX_MULTIPLY(5),             // 2 to 32
156
157         .CLKIN_DIVIDE_BY_2("FALSE"),
158         .CLKIN_PERIOD(20.0),
159         .CLKOUT_PHASE_SHIFT("NONE"),
160         .CLK_FEEDBACK("NONE"),
161         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
162         .DFS_FREQUENCY_MODE("LOW"),
163         .DLL_FREQUENCY_MODE("LOW"),
164         .DUTY_CYCLE_CORRECTION("TRUE"),
165         .PHASE_SHIFT(0),
166         .STARTUP_WAIT("TRUE")
167 ) clkgen_sys (
168         .CLK0(),
169         .CLK90(),
170         .CLK180(),
171         .CLK270(),
172
173         .CLK2X(),
174         .CLK2X180(),
175
176         .CLKDV(),
177         .CLKFX(sys_clk_dcm),
178         .CLKFX180(sys_clk_n_dcm),
179         .LOCKED(),
180         .CLKFB(),
181         .CLKIN(clk50),
182         .RST(1'b0),
183         .PSEN(1'b0)
184 );
185 AUTOBUF b1(
186         .I(sys_clk_dcm),
187         .O(sys_clk)
188 );
189 AUTOBUF b2(
190         .I(sys_clk_n_dcm),
191         .O(sys_clk_n)
192 );
193 `else
194 assign sys_clk = clkin;
195 assign sys_clk_n = ~clkin;
196 `endif
197
198 /* Debounce it and generate power-on reset. */
199 reg [19:0] rst_debounce;
200 reg sys_rst;
201 initial rst_debounce <= 20'hFFFFF;
202 initial sys_rst <= 1'b1;
203 always @(posedge sys_clk) begin
204         if(hard_reset)
205                 rst_debounce <= 20'hFFFFF;
206         else if(rst_debounce != 20'd0)
207                 rst_debounce <= rst_debounce - 20'd1;
208         sys_rst <= rst_debounce != 20'd0;
209 end
210
211 assign ac97_rst_n = ~sys_rst;
212 assign phy_rst_n = ~sys_rst;
213
214 /*
215  * We must release the Flash reset before the system reset
216  * because the Flash needs some time to come out of reset
217  * and the CPU begins fetching instructions from it
218  * as soon as the system reset is released.
219  * From datasheet, minimum reset pulse width is 100ns
220  * and reset-to-read time is 150ns.
221  */
222
223 reg [7:0] flash_rstcounter;
224 initial flash_rstcounter <= 8'd0;
225 always @(posedge sys_clk) begin
226         if(hard_reset)
227                 flash_rstcounter <= 8'd0;
228         else if(~flash_rstcounter[7])
229                 flash_rstcounter <= flash_rstcounter + 8'd1;
230 end
231
232 assign flash_rst_n = flash_rstcounter[7];
233
234 //------------------------------------------------------------------
235 // Wishbone master wires
236 //------------------------------------------------------------------
237 wire [31:0]     cpuibus_adr,
238                 cpudbus_adr,
239                 ac97bus_adr,
240                 pfpubus_adr,
241                 tmumbus_adr,
242                 ethernetrxbus_adr,
243                 ethernettxbus_adr;
244
245 wire [2:0]      cpuibus_cti,
246                 cpudbus_cti,
247                 ac97bus_cti,
248                 tmumbus_cti,
249                 ethernetrxbus_cti,
250                 ethernettxbus_cti;
251
252 wire [31:0]     cpuibus_dat_r,
253                 cpudbus_dat_r,
254                 cpudbus_dat_w,
255                 ac97bus_dat_r,
256                 ac97bus_dat_w,
257                 pfpubus_dat_w,
258                 tmumbus_dat_r,
259                 ethernetrxbus_dat_w,
260                 ethernettxbus_dat_r;
261
262 wire [3:0]      cpudbus_sel;
263
264 wire            cpudbus_we,
265                 ac97bus_we;
266
267 wire            cpuibus_cyc,
268                 cpudbus_cyc,
269                 ac97bus_cyc,
270                 pfpubus_cyc,
271                 tmumbus_cyc,
272                 ethernetrxbus_cyc,
273                 ethernettxbus_cyc;
274
275 wire            cpuibus_stb,
276                 cpudbus_stb,
277                 ac97bus_stb,
278                 pfpubus_stb,
279                 tmumbus_stb,
280                 ethernetrxbus_stb,
281                 ethernettxbus_stb;
282
283 wire            cpuibus_ack,
284                 cpudbus_ack,
285                 ac97bus_ack,
286                 tmumbus_ack,
287                 pfpubus_ack,
288                 ethernetrxbus_ack,
289                 ethernettxbus_ack;
290
291 //------------------------------------------------------------------
292 // Wishbone slave wires
293 //------------------------------------------------------------------
294 wire [31:0]     brg_adr,
295                 norflash_adr,
296                 csrbrg_adr;
297
298 wire [2:0]      brg_cti;
299
300 wire [31:0]     brg_dat_r,
301                 brg_dat_w,
302                 norflash_dat_r,
303                 csrbrg_dat_r,
304                 csrbrg_dat_w;
305
306 wire [3:0]      brg_sel;
307
308 wire            brg_we,
309                 csrbrg_we;
310
311 wire            brg_cyc,
312                 norflash_cyc,
313                 csrbrg_cyc;
314
315 wire            brg_stb,
316                 norflash_stb,
317                 csrbrg_stb;
318
319 wire            brg_ack,
320                 norflash_ack,
321                 csrbrg_ack;
322
323 //---------------------------------------------------------------------------
324 // Wishbone switch
325 //---------------------------------------------------------------------------
326 conbus #(
327         .s_addr_w(3),
328         .s0_addr(3'b000),       // norflash     0x00000000
329         .s1_addr(3'b001),       // free         0x20000000
330         .s2_addr(3'b010),       // FML bridge   0x40000000
331         .s3_addr(3'b100),       // CSR bridge   0x80000000
332         .s4_addr(3'b101)        // free         0xa0000000
333 ) conbus (
334         .sys_clk(sys_clk),
335         .sys_rst(sys_rst),
336
337         // Master 0
338         .m0_dat_i(32'hx),
339         .m0_dat_o(cpuibus_dat_r),
340         .m0_adr_i(cpuibus_adr),
341         .m0_cti_i(cpuibus_cti),
342         .m0_we_i(1'b0),
343         .m0_sel_i(4'hf),
344         .m0_cyc_i(cpuibus_cyc),
345         .m0_stb_i(cpuibus_stb),
346         .m0_ack_o(cpuibus_ack),
347         // Master 1
348         .m1_dat_i(cpudbus_dat_w),
349         .m1_dat_o(cpudbus_dat_r),
350         .m1_adr_i(cpudbus_adr),
351         .m1_cti_i(cpudbus_cti),
352         .m1_we_i(cpudbus_we),
353         .m1_sel_i(cpudbus_sel),
354         .m1_cyc_i(cpudbus_cyc),
355         .m1_stb_i(cpudbus_stb),
356         .m1_ack_o(cpudbus_ack),
357         // Master 2
358         .m2_dat_i(ac97bus_dat_w),
359         .m2_dat_o(ac97bus_dat_r),
360         .m2_adr_i(ac97bus_adr),
361         .m2_cti_i(ac97bus_cti),
362         .m2_we_i(ac97bus_we),
363         .m2_sel_i(4'hf),
364         .m2_cyc_i(ac97bus_cyc),
365         .m2_stb_i(ac97bus_stb),
366         .m2_ack_o(ac97bus_ack),
367         // Master 3
368         .m3_dat_i(pfpubus_dat_w),
369         .m3_dat_o(),
370         .m3_adr_i(pfpubus_adr),
371         .m3_cti_i(3'd0),
372         .m3_we_i(1'b1),
373         .m3_sel_i(4'hf),
374         .m3_cyc_i(pfpubus_cyc),
375         .m3_stb_i(pfpubus_stb),
376         .m3_ack_o(pfpubus_ack),
377         // Master 4
378         .m4_dat_i(32'bx),
379         .m4_dat_o(tmumbus_dat_r),
380         .m4_adr_i(tmumbus_adr),
381         .m4_cti_i(tmumbus_cti),
382         .m4_we_i(1'b0),
383         .m4_sel_i(4'hf),
384         .m4_cyc_i(tmumbus_cyc),
385         .m4_stb_i(tmumbus_stb),
386         .m4_ack_o(tmumbus_ack),
387         // Master 5
388         .m5_dat_i(ethernetrxbus_dat_w),
389         .m5_dat_o(),
390         .m5_adr_i(ethernetrxbus_adr),
391         .m5_cti_i(ethernetrxbus_cti),
392         .m5_we_i(1'b1),
393         .m5_sel_i(4'hf),
394         .m5_cyc_i(ethernetrxbus_cyc),
395         .m5_stb_i(ethernetrxbus_stb),
396         .m5_ack_o(ethernetrxbus_ack),
397         // Master 6
398         .m6_dat_i(),
399         .m6_dat_o(ethernettxbus_dat_r),
400         .m6_adr_i(ethernettxbus_adr),
401         .m6_cti_i(ethernettxbus_cti),
402         .m6_we_i(1'b0),
403         .m6_sel_i(4'hf),
404         .m6_cyc_i(ethernettxbus_cyc),
405         .m6_stb_i(ethernettxbus_stb),
406         .m6_ack_o(ethernettxbus_ack),
407
408         // Slave 0
409         .s0_dat_i(norflash_dat_r),
410         .s0_adr_o(norflash_adr),
411         .s0_cyc_o(norflash_cyc),
412         .s0_stb_o(norflash_stb),
413         .s0_ack_i(norflash_ack),
414         // Slave 1
415         .s1_dat_i(32'bx),
416         .s1_dat_o(),
417         .s1_adr_o(),
418         .s1_cti_o(),
419         .s1_sel_o(),
420         .s1_we_o(),
421         .s1_cyc_o(),
422         .s1_stb_o(),
423         .s1_ack_i(1'b0),
424         // Slave 2
425         .s2_dat_i(brg_dat_r),
426         .s2_dat_o(brg_dat_w),
427         .s2_adr_o(brg_adr),
428         .s2_cti_o(brg_cti),
429         .s2_sel_o(brg_sel),
430         .s2_we_o(brg_we),
431         .s2_cyc_o(brg_cyc),
432         .s2_stb_o(brg_stb),
433         .s2_ack_i(brg_ack),
434         // Slave 3
435         .s3_dat_i(csrbrg_dat_r),
436         .s3_dat_o(csrbrg_dat_w),
437         .s3_adr_o(csrbrg_adr),
438         .s3_we_o(csrbrg_we),
439         .s3_cyc_o(csrbrg_cyc),
440         .s3_stb_o(csrbrg_stb),
441         .s3_ack_i(csrbrg_ack),
442         // Slave 4
443         .s4_dat_i(32'bx),
444         .s4_dat_o(),
445         .s4_adr_o(),
446         .s4_we_o(),
447         .s4_cyc_o(),
448         .s4_stb_o(),
449         .s4_ack_i(1'b0)
450 );
451
452 //------------------------------------------------------------------
453 // CSR bus
454 //------------------------------------------------------------------
455 wire [13:0]     csr_a;
456 wire            csr_we;
457 wire [31:0]     csr_dw;
458 wire [31:0]     csr_dr_uart,
459                 csr_dr_sysctl,
460                 csr_dr_hpdmc,
461                 csr_dr_vga,
462                 csr_dr_ac97,
463                 csr_dr_pfpu,
464                 csr_dr_tmu,
465                 csr_dr_ethernet,
466                 csr_dr_fmlmeter;
467
468 //------------------------------------------------------------------
469 // FML master wires
470 //------------------------------------------------------------------
471 wire [`SDRAM_DEPTH-1:0] fml_brg_adr,
472                         fml_vga_adr,
473                         fml_tmur_adr,
474                         fml_tmudr_adr,
475                         fml_tmuw_adr;
476
477 wire                    fml_brg_stb,
478                         fml_vga_stb,
479                         fml_tmur_stb,
480                         fml_tmudr_stb,
481                         fml_tmuw_stb;
482
483 wire                    fml_brg_we;
484
485 wire                    fml_brg_ack,
486                         fml_vga_ack,
487                         fml_tmur_ack,
488                         fml_tmudr_ack,
489                         fml_tmuw_ack;
490
491 wire [7:0]              fml_brg_sel,
492                         fml_tmuw_sel;
493
494 wire [63:0]             fml_brg_dw,
495                         fml_tmuw_dw;
496
497 wire [63:0]             fml_brg_dr,
498                         fml_vga_dr,
499                         fml_tmur_dr,
500                         fml_tmudr_dr;
501
502 //------------------------------------------------------------------
503 // FML slave wires, to memory controller
504 //------------------------------------------------------------------
505 wire [`SDRAM_DEPTH-1:0] fml_adr;
506 wire fml_stb;
507 wire fml_we;
508 wire fml_ack;
509 wire [7:0] fml_sel;
510 wire [63:0] fml_dw;
511 wire [63:0] fml_dr;
512
513 //---------------------------------------------------------------------------
514 // FML arbiter
515 //---------------------------------------------------------------------------
516 fmlarb #(
517         .fml_depth(`SDRAM_DEPTH)
518 ) fmlarb (
519         .sys_clk(sys_clk),
520         .sys_rst(sys_rst),
521
522         /* VGA framebuffer (high priority) */
523         .m0_adr(fml_vga_adr),
524         .m0_stb(fml_vga_stb),
525         .m0_we(1'b0),
526         .m0_ack(fml_vga_ack),
527         .m0_sel(8'bx),
528         .m0_di(64'bx),
529         .m0_do(fml_vga_dr),
530
531         /* WISHBONE bridge */
532         .m1_adr(fml_brg_adr),
533         .m1_stb(fml_brg_stb),
534         .m1_we(fml_brg_we),
535         .m1_ack(fml_brg_ack),
536         .m1_sel(fml_brg_sel),
537         .m1_di(fml_brg_dw),
538         .m1_do(fml_brg_dr),
539
540         /* TMU, pixel read DMA (texture) */
541         .m2_adr(fml_tmur_adr),
542         .m2_stb(fml_tmur_stb),
543         .m2_we(1'b0),
544         .m2_ack(fml_tmur_ack),
545         .m2_sel(8'bx),
546         .m2_di(64'bx),
547         .m2_do(fml_tmur_dr),
548
549         /* TMU, pixel write DMA */
550         .m3_adr(fml_tmuw_adr),
551         .m3_stb(fml_tmuw_stb),
552         .m3_we(1'b1),
553         .m3_ack(fml_tmuw_ack),
554         .m3_sel(fml_tmuw_sel),
555         .m3_di(fml_tmuw_dw),
556         .m3_do(),
557
558         /* TMU, pixel read DMA (destination) */
559         .m4_adr(fml_tmudr_adr),
560         .m4_stb(fml_tmudr_stb),
561         .m4_we(1'b0),
562         .m4_ack(fml_tmudr_ack),
563         .m4_sel(8'bx),
564         .m4_di(64'bx),
565         .m4_do(fml_tmudr_dr),
566
567         .s_adr(fml_adr),
568         .s_stb(fml_stb),
569         .s_we(fml_we),
570         .s_ack(fml_ack),
571         .s_sel(fml_sel),
572         .s_di(fml_dr),
573         .s_do(fml_dw)
574 );
575
576 //---------------------------------------------------------------------------
577 // WISHBONE to CSR bridge
578 //---------------------------------------------------------------------------
579 csrbrg csrbrg(
580         .sys_clk(sys_clk),
581         .sys_rst(sys_rst),
582         
583         .wb_adr_i(csrbrg_adr),
584         .wb_dat_i(csrbrg_dat_w),
585         .wb_dat_o(csrbrg_dat_r),
586         .wb_cyc_i(csrbrg_cyc),
587         .wb_stb_i(csrbrg_stb),
588         .wb_we_i(csrbrg_we),
589         .wb_ack_o(csrbrg_ack),
590         
591         .csr_a(csr_a),
592         .csr_we(csr_we),
593         .csr_do(csr_dw),
594         /* combine all slave->master data lines with an OR */
595         .csr_di(
596                  csr_dr_uart
597                 |csr_dr_sysctl
598                 |csr_dr_hpdmc
599                 |csr_dr_vga
600                 |csr_dr_ac97
601                 |csr_dr_pfpu
602                 |csr_dr_tmu
603                 |csr_dr_ethernet
604                 |csr_dr_fmlmeter
605         )
606 );
607
608 //---------------------------------------------------------------------------
609 // WISHBONE to FML bridge
610 //---------------------------------------------------------------------------
611 wire dcb_stb;
612 wire [`SDRAM_DEPTH-1:0] dcb_adr;
613 wire [63:0] dcb_dat;
614 wire dcb_hit;
615
616 fmlbrg #(
617         .fml_depth(`SDRAM_DEPTH)
618 ) fmlbrg (
619         .sys_clk(sys_clk),
620         .sys_rst(sys_rst),
621         
622         .wb_adr_i(brg_adr),
623         .wb_cti_i(brg_cti),
624         .wb_dat_o(brg_dat_r),
625         .wb_dat_i(brg_dat_w),
626         .wb_sel_i(brg_sel),
627         .wb_stb_i(brg_stb),
628         .wb_cyc_i(brg_cyc),
629         .wb_ack_o(brg_ack),
630         .wb_we_i(brg_we),
631         
632         .fml_adr(fml_brg_adr),
633         .fml_stb(fml_brg_stb),
634         .fml_we(fml_brg_we),
635         .fml_ack(fml_brg_ack),
636         .fml_sel(fml_brg_sel),
637         .fml_di(fml_brg_dr),
638         .fml_do(fml_brg_dw),
639
640         .dcb_stb(dcb_stb),
641         .dcb_adr(dcb_adr),
642         .dcb_dat(dcb_dat),
643         .dcb_hit(dcb_hit)
644 );
645
646 //---------------------------------------------------------------------------
647 // Interrupts
648 //---------------------------------------------------------------------------
649 wire gpio_irq;
650 wire timer0_irq;
651 wire timer1_irq;
652 wire uartrx_irq;
653 wire uarttx_irq;
654 wire ac97crrequest_irq;
655 wire ac97crreply_irq;
656 wire ac97dmar_irq;
657 wire ac97dmaw_irq;
658 wire pfpu_irq;
659 wire tmu_irq;
660 wire ethernetrx_irq;
661 wire ethernettx_irq;
662
663 wire [31:0] cpu_interrupt;
664 assign cpu_interrupt = {19'd0,
665         ethernettx_irq,
666         ethernetrx_irq,
667         tmu_irq,
668         pfpu_irq,
669         ac97dmaw_irq,
670         ac97dmar_irq,
671         ac97crreply_irq,
672         ac97crrequest_irq,
673         uarttx_irq,
674         uartrx_irq,
675         timer1_irq,
676         timer0_irq,
677         gpio_irq
678 };
679
680 //---------------------------------------------------------------------------
681 // LM32 CPU
682 //---------------------------------------------------------------------------
683 lm32_top cpu(
684         .clk_i(sys_clk),
685         .rst_i(sys_rst),
686         .interrupt(cpu_interrupt),
687
688         .I_ADR_O(cpuibus_adr),
689         .I_DAT_I(cpuibus_dat_r),
690         .I_DAT_O(),
691         .I_SEL_O(),
692         .I_CYC_O(cpuibus_cyc),
693         .I_STB_O(cpuibus_stb),
694         .I_ACK_I(cpuibus_ack),
695         .I_WE_O(),
696         .I_CTI_O(cpuibus_cti),
697         .I_LOCK_O(),
698         .I_BTE_O(),
699         .I_ERR_I(1'b0),
700         .I_RTY_I(1'b0),
701
702         .D_ADR_O(cpudbus_adr),
703         .D_DAT_I(cpudbus_dat_r),
704         .D_DAT_O(cpudbus_dat_w),
705         .D_SEL_O(cpudbus_sel),
706         .D_CYC_O(cpudbus_cyc),
707         .D_STB_O(cpudbus_stb),
708         .D_ACK_I(cpudbus_ack),
709         .D_WE_O (cpudbus_we),
710         .D_CTI_O(cpudbus_cti),
711         .D_LOCK_O(),
712         .D_BTE_O(),
713         .D_ERR_I(1'b0),
714         .D_RTY_I(1'b0)
715 );
716
717 //---------------------------------------------------------------------------
718 // Boot ROM
719 //---------------------------------------------------------------------------
720 norflash16 #(
721         .adr_width(24)
722 ) norflash (
723         .sys_clk(sys_clk),
724         .sys_rst(sys_rst),
725
726         .wb_adr_i(norflash_adr),
727         .wb_dat_o(norflash_dat_r),
728         .wb_stb_i(norflash_stb),
729         .wb_cyc_i(norflash_cyc),
730         .wb_ack_o(norflash_ack),
731         
732         .flash_adr(flash_adr),
733         .flash_d(flash_d)
734 );
735
736 assign flash_oe_n = 1'b0;
737 assign flash_we_n = 1'b1;
738 assign flash_ce_n = 1'b0;
739
740 //---------------------------------------------------------------------------
741 // UART
742 //---------------------------------------------------------------------------
743 uart #(
744         .csr_addr(4'h0),
745         .clk_freq(`CLOCK_FREQUENCY),
746         .baud(`BAUD_RATE)
747 ) uart (
748         .sys_clk(sys_clk),
749         .sys_rst(sys_rst),
750
751         .csr_a(csr_a),
752         .csr_we(csr_we),
753         .csr_di(csr_dw),
754         .csr_do(csr_dr_uart),
755         
756         .rx_irq(uartrx_irq),
757         .tx_irq(uarttx_irq),
758         
759         .uart_rxd(uart_rx),
760         .uart_txd(uart_tx)
761 );
762
763 //---------------------------------------------------------------------------
764 // System Controller
765 //---------------------------------------------------------------------------
766 wire [13:0] gpio_outputs;
767 wire [31:0] capabilities;
768
769 sysctl #(
770         .csr_addr(4'h1),
771         .ninputs(3),
772         .noutputs(2),
773         .systemid(32'h4D4F4E45) /* MONE */
774 ) sysctl (
775         .sys_clk(sys_clk),
776         .sys_rst(sys_rst),
777
778         .gpio_irq(gpio_irq),
779         .timer0_irq(timer0_irq),
780         .timer1_irq(timer1_irq),
781
782         .csr_a(csr_a),
783         .csr_we(csr_we),
784         .csr_di(csr_dw),
785         .csr_do(csr_dr_sysctl),
786
787         .gpio_inputs({btn3, btn2, btn1}),
788         .gpio_outputs({led2, led1}),
789
790         .capabilities(capabilities),
791         .hard_reset(hard_reset)
792 );
793
794 gen_capabilities gen_capabilities(
795         .capabilities(capabilities)
796 );
797
798 //---------------------------------------------------------------------------
799 // DDR SDRAM
800 //---------------------------------------------------------------------------
801 ddram #(
802         .csr_addr(4'h2)
803 ) ddram (
804         .sys_clk(sys_clk),
805         .sys_clk_n(sys_clk_n),
806         .sys_rst(sys_rst),
807
808         .csr_a(csr_a),
809         .csr_we(csr_we),
810         .csr_di(csr_dw),
811         .csr_do(csr_dr_hpdmc),
812
813         .fml_adr(fml_adr),
814         .fml_stb(fml_stb),
815         .fml_we(fml_we),
816         .fml_ack(fml_ack),
817         .fml_sel(fml_sel),
818         .fml_di(fml_dw),
819         .fml_do(fml_dr),
820         
821         .sdram_clk_p(sdram_clk_p),
822         .sdram_clk_n(sdram_clk_n),
823         .sdram_cke(sdram_cke),
824         .sdram_cs_n(sdram_cs_n),
825         .sdram_we_n(sdram_we_n),
826         .sdram_cas_n(sdram_cas_n),
827         .sdram_ras_n(sdram_ras_n),
828         .sdram_dqm(sdram_dm),
829         .sdram_adr(sdram_adr),
830         .sdram_ba(sdram_ba),
831         .sdram_dq(sdram_dq),
832         .sdram_dqs(sdram_dqs)
833 );
834
835 //---------------------------------------------------------------------------
836 // VGA
837 //---------------------------------------------------------------------------
838 vga #(
839         .csr_addr(4'h3),
840         .fml_depth(`SDRAM_DEPTH)
841 ) vga (
842         .sys_clk(sys_clk),
843         .sys_rst(sys_rst),
844         
845         .csr_a(csr_a),
846         .csr_we(csr_we),
847         .csr_di(csr_dw),
848         .csr_do(csr_dr_vga),
849         
850         .fml_adr(fml_vga_adr),
851         .fml_stb(fml_vga_stb),
852         .fml_ack(fml_vga_ack),
853         .fml_di(fml_vga_dr),
854
855         .dcb_stb(dcb_stb),
856         .dcb_adr(dcb_adr),
857         .dcb_dat(dcb_dat),
858         .dcb_hit(dcb_hit),
859         
860         .vga_psave_n(vga_psave_n),
861         .vga_hsync_n(vga_hsync_n),
862         .vga_vsync_n(vga_vsync_n),
863         .vga_r(vga_r),
864         .vga_g(vga_g),
865         .vga_b(vga_b),
866         .vga_clk(vga_clk)
867 );
868
869 //---------------------------------------------------------------------------
870 // AC97
871 //---------------------------------------------------------------------------
872 `ifdef ENABLE_AC97
873 wire ac97_clk_b;
874 BUFG b_ac97(
875         .I(ac97_clk),
876         .O(ac97_clk_b)
877 );
878 ac97 #(
879         .csr_addr(4'h4)
880 ) ac97 (
881         .sys_clk(sys_clk),
882         .sys_rst(sys_rst),
883         .ac97_clk(ac97_clk_b),
884         .ac97_rst_n(ac97_rst_n),
885         
886         .ac97_sin(ac97_sin),
887         .ac97_sout(ac97_sout),
888         .ac97_sync(ac97_sync),
889         
890         .csr_a(csr_a),
891         .csr_we(csr_we),
892         .csr_di(csr_dw),
893         .csr_do(csr_dr_ac97),
894         
895         .crrequest_irq(ac97crrequest_irq),
896         .crreply_irq(ac97crreply_irq),
897         .dmar_irq(ac97dmar_irq),
898         .dmaw_irq(ac97dmaw_irq),
899         
900         .wbm_adr_o(ac97bus_adr),
901         .wbm_cti_o(ac97bus_cti),
902         .wbm_we_o(ac97bus_we),
903         .wbm_cyc_o(ac97bus_cyc),
904         .wbm_stb_o(ac97bus_stb),
905         .wbm_ack_i(ac97bus_ack),
906         .wbm_dat_i(ac97bus_dat_r),
907         .wbm_dat_o(ac97bus_dat_w)
908 );
909
910 `else
911 assign csr_dr_ac97 = 32'd0;
912
913 assign ac97crrequest_irq = 1'b0;
914 assign ac97crreply_irq = 1'b0;
915 assign ac97dmar_irq = 1'b0;
916 assign ac97dmaw_irq = 1'b0;
917
918 assign ac97_sout = 1'b0;
919 assign ac97_sync = 1'b0;
920
921 assign ac97bus_adr = 32'bx;
922 assign ac97bus_cti = 3'bx;
923 assign ac97bus_we = 1'bx;
924 assign ac97bus_cyc = 1'b0;
925 assign ac97bus_stb = 1'b0;
926 assign ac97bus_dat_w = 32'bx;
927 `endif
928
929 //---------------------------------------------------------------------------
930 // Programmable FPU
931 //---------------------------------------------------------------------------
932 `ifdef ENABLE_PFPU
933 pfpu #(
934         .csr_addr(4'h5)
935 ) pfpu (
936         .sys_clk(sys_clk),
937         .sys_rst(sys_rst),
938         
939         .csr_a(csr_a),
940         .csr_we(csr_we),
941         .csr_di(csr_dw),
942         .csr_do(csr_dr_pfpu),
943         
944         .irq(pfpu_irq),
945         
946         .wbm_dat_o(pfpubus_dat_w),
947         .wbm_adr_o(pfpubus_adr),
948         .wbm_cyc_o(pfpubus_cyc),
949         .wbm_stb_o(pfpubus_stb),
950         .wbm_ack_i(pfpubus_ack)
951 );
952
953 `else
954 assign csr_dr_pfpu = 32'd0;
955
956 assign pfpu_irq = 1'b0;
957
958 assign pfpubus_dat_w = 32'hx;
959 assign pfpubus_adr = 32'hx;
960 assign pfpubus_cyc = 1'b0;
961 assign pfpubus_stb = 1'b0;
962 `endif
963
964 //---------------------------------------------------------------------------
965 // Texture Mapping Unit
966 //---------------------------------------------------------------------------
967 `ifdef ENABLE_TMU
968 tmu2 #(
969         .csr_addr(4'h6),
970         .fml_depth(`SDRAM_DEPTH)
971 ) tmu (
972         .sys_clk(sys_clk),
973         .sys_rst(sys_rst),
974
975         .csr_a(csr_a),
976         .csr_we(csr_we),
977         .csr_di(csr_dw),
978         .csr_do(csr_dr_tmu),
979
980         .irq(tmu_irq),
981
982         .wbm_adr_o(tmumbus_adr),
983         .wbm_cti_o(tmumbus_cti),
984         .wbm_cyc_o(tmumbus_cyc),
985         .wbm_stb_o(tmumbus_stb),
986         .wbm_ack_i(tmumbus_ack),
987         .wbm_dat_i(tmumbus_dat_r),
988
989         .fmlr_adr(fml_tmur_adr),
990         .fmlr_stb(fml_tmur_stb),
991         .fmlr_ack(fml_tmur_ack),
992         .fmlr_di(fml_tmur_dr),
993
994         .fmldr_adr(fml_tmudr_adr),
995         .fmldr_stb(fml_tmudr_stb),
996         .fmldr_ack(fml_tmudr_ack),
997         .fmldr_di(fml_tmudr_dr),
998
999         .fmlw_adr(fml_tmuw_adr),
1000         .fmlw_stb(fml_tmuw_stb),
1001         .fmlw_ack(fml_tmuw_ack),
1002         .fmlw_sel(fml_tmuw_sel),
1003         .fmlw_do(fml_tmuw_dw)
1004 );
1005
1006 `else
1007 assign csr_dr_tmu = 32'd0;
1008
1009 assign tmu_irq = 1'b0;
1010
1011 assign tmumbus_adr = 32'hx;
1012 assign tmumbus_cti = 3'bxxx;
1013 assign tmumbus_cyc = 1'b0;
1014 assign tmumbus_stb = 1'b0;
1015
1016 assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
1017 assign fml_tmur_stb = 1'b0;
1018
1019 assign fml_tmudr_adr = {`SDRAM_DEPTH{1'bx}};
1020 assign fml_tmudr_stb = 1'b0;
1021
1022 assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
1023 assign fml_tmuw_stb = 1'b0;
1024 assign fml_tmuw_sel = 8'bx;
1025 assign fml_tmuw_dw = 64'bx;
1026 `endif
1027
1028 //---------------------------------------------------------------------------
1029 // Ethernet
1030 //---------------------------------------------------------------------------
1031 `ifdef ENABLE_ETHERNET
1032 wire phy_tx_clk_b0;
1033 wire phy_tx_clk_b;
1034 BUFIO2 b_phy_tx_clk0(
1035         .I(phy_tx_clk),
1036         .DIVCLK(phy_tx_clk_b0)
1037 );
1038 BUFG b_phy_tx_clk(
1039         .I(phy_tx_clk_b0),
1040         .O(phy_tx_clk_b)
1041 );
1042 wire phy_rx_clk_b0;
1043 wire phy_rx_clk_b;
1044 BUFIO2 b_phy_rx_clk0(
1045         .I(phy_rx_clk),
1046         .DIVCLK(phy_rx_clk_b0)
1047 );
1048 BUFG b_phy_rx_clk(
1049         .I(phy_rx_clk_b0),
1050         .O(phy_rx_clk_b)
1051 );
1052 minimac #(
1053         .csr_addr(4'h9)
1054 ) ethernet (
1055         .sys_clk(sys_clk),
1056         .sys_rst(sys_rst),
1057
1058         .csr_a(csr_a),
1059         .csr_we(csr_we),
1060         .csr_di(csr_dw),
1061         .csr_do(csr_dr_ethernet),
1062
1063         .wbrx_adr_o(ethernetrxbus_adr),
1064         .wbrx_cti_o(ethernetrxbus_cti),
1065         .wbrx_cyc_o(ethernetrxbus_cyc),
1066         .wbrx_stb_o(ethernetrxbus_stb),
1067         .wbrx_ack_i(ethernetrxbus_ack),
1068         .wbrx_dat_o(ethernetrxbus_dat_w),
1069
1070         .wbtx_adr_o(ethernettxbus_adr),
1071         .wbtx_cti_o(ethernettxbus_cti),
1072         .wbtx_cyc_o(ethernettxbus_cyc),
1073         .wbtx_stb_o(ethernettxbus_stb),
1074         .wbtx_ack_i(ethernettxbus_ack),
1075         .wbtx_dat_i(ethernettxbus_dat_r),
1076
1077         .irq_rx(ethernetrx_irq),
1078         .irq_tx(ethernettx_irq),
1079
1080         .phy_tx_clk(phy_tx_clk_b),
1081         .phy_tx_data(phy_tx_data),
1082         .phy_tx_en(phy_tx_en),
1083         .phy_tx_er(phy_tx_er),
1084         .phy_rx_clk(phy_rx_clk_b),
1085         .phy_rx_data(phy_rx_data),
1086         .phy_dv(phy_dv),
1087         .phy_rx_er(phy_rx_er),
1088         .phy_col(phy_col),
1089         .phy_crs(phy_crs),
1090         .phy_mii_clk(phy_mii_clk),
1091         .phy_mii_data(phy_mii_data)
1092 );
1093 `else
1094 assign csr_dr_ethernet = 32'd0;
1095 assign ethernetrxbus_adr = 32'bx;
1096 assign ethernetrxbus_cti = 3'bx;
1097 assign ethernetrxbus_cyc = 1'b0;
1098 assign ethernetrxbus_stb = 1'b0;
1099 assign ethernetrxbus_dat_w = 32'bx;
1100 assign ethernettxbus_adr = 32'bx;
1101 assign ethernettxbus_cti = 3'bx;
1102 assign ethernettxbus_cyc = 1'b0;
1103 assign ethernettxbus_stb = 1'b0;
1104 assign ethernettxbus_dat_r = 32'bx;
1105 assign ethernetrx_irq = 1'b0;
1106 assign ethernettx_irq = 1'b0;
1107 assign phy_tx_data = 4'b0;
1108 assign phy_tx_en = 1'b0;
1109 assign phy_tx_er = 1'b0;
1110 assign phy_mii_clk = 1'b0;
1111 assign phy_mii_data = 1'bz;
1112 `endif
1113
1114 always @(posedge clk50) phy_clk <= ~phy_clk;
1115
1116 //---------------------------------------------------------------------------
1117 // FastMemoryLink usage and performance meter
1118 //---------------------------------------------------------------------------
1119 `ifdef ENABLE_FMLMETER
1120 fmlmeter #(
1121         .csr_addr(4'ha)
1122 ) fmlmeter (
1123         .sys_clk(sys_clk),
1124         .sys_rst(sys_rst),
1125
1126         .csr_a(csr_a),
1127         .csr_we(csr_we),
1128         .csr_di(csr_dw),
1129         .csr_do(csr_dr_fmlmeter),
1130
1131         .fml_stb(fml_stb),
1132         .fml_ack(fml_ack)
1133 );
1134 `else
1135 assign csr_dr_fmlmeter = 32'd0;
1136 `endif
1137
1138 // TODO
1139 assign vga_sda = 1'b0;
1140 assign vga_sdc = 1'b0;
1141
1142 assign mc_d[3:0] = 4'bz;
1143 assign mc_cmd = 1'bz;
1144 assign mc_clk = 1'b0;
1145
1146 assign usba_spd = 1'b0;
1147 assign usba_oe_n = 1'b0;
1148 assign usba_vp = 1'bz;
1149 assign usba_vm = 1'bz;
1150 assign usbb_spd = 1'b0;
1151 assign usbb_oe_n = 1'b0;
1152 assign usbb_vp = 1'bz;
1153 assign usbb_vm = 1'bz;
1154
1155 assign videoin_sda = 1'bz;
1156 assign videoin_sdc = 1'b0;
1157
1158 assign midi_tx = 1'b0;
1159
1160 assign dmxa_de = 1'b0;
1161 assign dmxa_d = 1'b0;
1162 assign dmxb_de = 1'b0;
1163 assign dmxb_d = 1'b0;
1164
1165 endmodule