VGA DDC (not fully tested)
[mw/milkymist.git] / boards / milkymist-one / rtl / system.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module system(
21         input clk50,
22         
23         // Boot ROM
24         output [23:0] flash_adr,
25         input [15:0] flash_d,
26         output flash_oe_n,
27         output flash_we_n,
28         output flash_ce_n,
29         output flash_rst_n,
30         input flash_sts,
31
32         // UART
33         input uart_rx,
34         output uart_tx,
35
36         // GPIO
37         input btn1,
38         input btn2,
39         input btn3,
40         output led1,
41         output led2,
42
43         // DDR SDRAM
44         output sdram_clk_p,
45         output sdram_clk_n,
46         output sdram_cke,
47         output sdram_cs_n,
48         output sdram_we_n,
49         output sdram_cas_n,
50         output sdram_ras_n,
51         output [3:0] sdram_dm,
52         output [12:0] sdram_adr,
53         output [1:0] sdram_ba,
54         inout [31:0] sdram_dq,
55         inout [3:0] sdram_dqs,
56
57         // VGA
58         output vga_psave_n,
59         output vga_hsync_n,
60         output vga_vsync_n,
61         output [7:0] vga_r,
62         output [7:0] vga_g,
63         output [7:0] vga_b,
64         output vga_clk,
65         inout vga_sda,
66         output vga_sdc,
67
68         // Memory card
69         inout [3:0] mc_d,
70         inout mc_cmd,
71         output mc_clk,
72         
73         // AC97
74         input ac97_clk,
75         input ac97_sin,
76         output ac97_sout,
77         output ac97_sync,
78         output ac97_rst_n,
79
80         // USB
81         output usba_spd,
82         output usba_oe_n,
83         input usba_rcv,
84         inout usba_vp,
85         inout usba_vm,
86
87         output usbb_spd,
88         output usbb_oe_n,
89         input usbb_rcv,
90         inout usbb_vp,
91         inout usbb_vm,
92
93         // Ethernet
94         output phy_rst_n,
95         input phy_tx_clk,
96         output [3:0] phy_tx_data,
97         output phy_tx_en,
98         output phy_tx_er,
99         input phy_rx_clk,
100         input [3:0] phy_rx_data,
101         input phy_dv,
102         input phy_rx_er,
103         input phy_col,
104         input phy_crs,
105         input phy_irq_n,
106         output phy_mii_clk,
107         inout phy_mii_data,
108         output reg phy_clk,
109
110         // Video Input
111         input [7:0] videoin_p,
112         input videoin_hs,
113         input videoin_vs,
114         input videoin_field,
115         input videoin_llc,
116         input videoin_irq_n,
117         output videoin_rst_n,
118         inout videoin_sda,
119         output videoin_sdc,
120
121         // MIDI
122         output midi_tx,
123         input midi_rx,
124
125         // DMX512
126         input dmxa_r,
127         output dmxa_de,
128         output dmxa_d,
129         input dmxb_r,
130         output dmxb_de,
131         output dmxb_d,
132
133         // IR
134         input ir_rx,
135
136         // Expansion connector
137         input [11:0] exp
138 );
139
140 //------------------------------------------------------------------
141 // Clock and Reset Generation
142 //------------------------------------------------------------------
143 wire sys_clk;
144 wire sys_clk_n;
145 wire hard_reset;
146 wire reset_button = btn1 & btn2 & btn3;
147
148 `ifndef SIMULATION
149 wire sys_clk_dcm;
150 wire sys_clk_n_dcm;
151
152 DCM_SP #(
153         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
154
155         .CLKFX_DIVIDE(3),               // 1 to 32
156         .CLKFX_MULTIPLY(5),             // 2 to 32
157
158         .CLKIN_DIVIDE_BY_2("FALSE"),
159         .CLKIN_PERIOD(20.0),
160         .CLKOUT_PHASE_SHIFT("NONE"),
161         .CLK_FEEDBACK("NONE"),
162         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
163         .DFS_FREQUENCY_MODE("LOW"),
164         .DLL_FREQUENCY_MODE("LOW"),
165         .DUTY_CYCLE_CORRECTION("TRUE"),
166         .PHASE_SHIFT(0),
167         .STARTUP_WAIT("TRUE")
168 ) clkgen_sys (
169         .CLK0(),
170         .CLK90(),
171         .CLK180(),
172         .CLK270(),
173
174         .CLK2X(),
175         .CLK2X180(),
176
177         .CLKDV(),
178         .CLKFX(sys_clk_dcm),
179         .CLKFX180(sys_clk_n_dcm),
180         .LOCKED(),
181         .CLKFB(),
182         .CLKIN(clk50),
183         .RST(1'b0),
184         .PSEN(1'b0)
185 );
186 BUFG b1(
187         .I(sys_clk_dcm),
188         .O(sys_clk)
189 );
190 BUFG b2(
191         .I(sys_clk_n_dcm),
192         .O(sys_clk_n)
193 );
194 `else
195 assign sys_clk = clkin;
196 assign sys_clk_n = ~clkin;
197 `endif
198
199 reg trigger_reset;
200 always @(posedge sys_clk) trigger_reset <= hard_reset|reset_button;
201 reg [19:0] rst_debounce;
202 reg sys_rst;
203 initial rst_debounce <= 20'hFFFFF;
204 initial sys_rst <= 1'b1;
205 always @(posedge sys_clk) begin
206         if(trigger_reset)
207                 rst_debounce <= 20'hFFFFF;
208         else if(rst_debounce != 20'd0)
209                 rst_debounce <= rst_debounce - 20'd1;
210         sys_rst <= rst_debounce != 20'd0;
211 end
212
213 assign ac97_rst_n = ~sys_rst;
214 assign phy_rst_n = ~sys_rst;
215 assign videoin_rst_n = ~sys_rst;
216
217 /*
218  * We must release the Flash reset before the system reset
219  * because the Flash needs some time to come out of reset
220  * and the CPU begins fetching instructions from it
221  * as soon as the system reset is released.
222  * From datasheet, minimum reset pulse width is 100ns
223  * and reset-to-read time is 150ns.
224  */
225
226 reg [7:0] flash_rstcounter;
227 initial flash_rstcounter <= 8'd0;
228 always @(posedge sys_clk) begin
229         if(trigger_reset)
230                 flash_rstcounter <= 8'd0;
231         else if(~flash_rstcounter[7])
232                 flash_rstcounter <= flash_rstcounter + 8'd1;
233 end
234
235 assign flash_rst_n = flash_rstcounter[7];
236
237 //------------------------------------------------------------------
238 // Wishbone master wires
239 //------------------------------------------------------------------
240 wire [31:0]     cpuibus_adr,
241                 cpudbus_adr,
242                 ac97bus_adr,
243                 pfpubus_adr,
244                 tmumbus_adr,
245                 ethernetrxbus_adr,
246                 ethernettxbus_adr;
247
248 wire [2:0]      cpuibus_cti,
249                 cpudbus_cti,
250                 ac97bus_cti,
251                 tmumbus_cti,
252                 ethernetrxbus_cti,
253                 ethernettxbus_cti;
254
255 wire [31:0]     cpuibus_dat_r,
256                 cpudbus_dat_r,
257                 cpudbus_dat_w,
258                 ac97bus_dat_r,
259                 ac97bus_dat_w,
260                 pfpubus_dat_w,
261                 tmumbus_dat_r,
262                 ethernetrxbus_dat_w,
263                 ethernettxbus_dat_r;
264
265 wire [3:0]      cpudbus_sel;
266
267 wire            cpudbus_we,
268                 ac97bus_we;
269
270 wire            cpuibus_cyc,
271                 cpudbus_cyc,
272                 ac97bus_cyc,
273                 pfpubus_cyc,
274                 tmumbus_cyc,
275                 ethernetrxbus_cyc,
276                 ethernettxbus_cyc;
277
278 wire            cpuibus_stb,
279                 cpudbus_stb,
280                 ac97bus_stb,
281                 pfpubus_stb,
282                 tmumbus_stb,
283                 ethernetrxbus_stb,
284                 ethernettxbus_stb;
285
286 wire            cpuibus_ack,
287                 cpudbus_ack,
288                 ac97bus_ack,
289                 tmumbus_ack,
290                 pfpubus_ack,
291                 ethernetrxbus_ack,
292                 ethernettxbus_ack;
293
294 //------------------------------------------------------------------
295 // Wishbone slave wires
296 //------------------------------------------------------------------
297 wire [31:0]     brg_adr,
298                 norflash_adr,
299                 csrbrg_adr;
300
301 wire [2:0]      brg_cti;
302
303 wire [31:0]     brg_dat_r,
304                 brg_dat_w,
305                 norflash_dat_r,
306                 csrbrg_dat_r,
307                 csrbrg_dat_w;
308
309 wire [3:0]      brg_sel;
310
311 wire            brg_we,
312                 csrbrg_we;
313
314 wire            brg_cyc,
315                 norflash_cyc,
316                 csrbrg_cyc;
317
318 wire            brg_stb,
319                 norflash_stb,
320                 csrbrg_stb;
321
322 wire            brg_ack,
323                 norflash_ack,
324                 csrbrg_ack;
325
326 //---------------------------------------------------------------------------
327 // Wishbone switch
328 //---------------------------------------------------------------------------
329 conbus #(
330         .s_addr_w(3),
331         .s0_addr(3'b000),       // norflash     0x00000000
332         .s1_addr(3'b001),       // free         0x20000000
333         .s2_addr(3'b010),       // FML bridge   0x40000000
334         .s3_addr(3'b100),       // CSR bridge   0x80000000
335         .s4_addr(3'b101)        // free         0xa0000000
336 ) conbus (
337         .sys_clk(sys_clk),
338         .sys_rst(sys_rst),
339
340         // Master 0
341         .m0_dat_i(32'hx),
342         .m0_dat_o(cpuibus_dat_r),
343         .m0_adr_i(cpuibus_adr),
344         .m0_cti_i(cpuibus_cti),
345         .m0_we_i(1'b0),
346         .m0_sel_i(4'hf),
347         .m0_cyc_i(cpuibus_cyc),
348         .m0_stb_i(cpuibus_stb),
349         .m0_ack_o(cpuibus_ack),
350         // Master 1
351         .m1_dat_i(cpudbus_dat_w),
352         .m1_dat_o(cpudbus_dat_r),
353         .m1_adr_i(cpudbus_adr),
354         .m1_cti_i(cpudbus_cti),
355         .m1_we_i(cpudbus_we),
356         .m1_sel_i(cpudbus_sel),
357         .m1_cyc_i(cpudbus_cyc),
358         .m1_stb_i(cpudbus_stb),
359         .m1_ack_o(cpudbus_ack),
360         // Master 2
361         .m2_dat_i(ac97bus_dat_w),
362         .m2_dat_o(ac97bus_dat_r),
363         .m2_adr_i(ac97bus_adr),
364         .m2_cti_i(ac97bus_cti),
365         .m2_we_i(ac97bus_we),
366         .m2_sel_i(4'hf),
367         .m2_cyc_i(ac97bus_cyc),
368         .m2_stb_i(ac97bus_stb),
369         .m2_ack_o(ac97bus_ack),
370         // Master 3
371         .m3_dat_i(pfpubus_dat_w),
372         .m3_dat_o(),
373         .m3_adr_i(pfpubus_adr),
374         .m3_cti_i(3'd0),
375         .m3_we_i(1'b1),
376         .m3_sel_i(4'hf),
377         .m3_cyc_i(pfpubus_cyc),
378         .m3_stb_i(pfpubus_stb),
379         .m3_ack_o(pfpubus_ack),
380         // Master 4
381         .m4_dat_i(32'bx),
382         .m4_dat_o(tmumbus_dat_r),
383         .m4_adr_i(tmumbus_adr),
384         .m4_cti_i(tmumbus_cti),
385         .m4_we_i(1'b0),
386         .m4_sel_i(4'hf),
387         .m4_cyc_i(tmumbus_cyc),
388         .m4_stb_i(tmumbus_stb),
389         .m4_ack_o(tmumbus_ack),
390         // Master 5
391         .m5_dat_i(ethernetrxbus_dat_w),
392         .m5_dat_o(),
393         .m5_adr_i(ethernetrxbus_adr),
394         .m5_cti_i(ethernetrxbus_cti),
395         .m5_we_i(1'b1),
396         .m5_sel_i(4'hf),
397         .m5_cyc_i(ethernetrxbus_cyc),
398         .m5_stb_i(ethernetrxbus_stb),
399         .m5_ack_o(ethernetrxbus_ack),
400         // Master 6
401         .m6_dat_i(32'bx),
402         .m6_dat_o(ethernettxbus_dat_r),
403         .m6_adr_i(ethernettxbus_adr),
404         .m6_cti_i(ethernettxbus_cti),
405         .m6_we_i(1'b0),
406         .m6_sel_i(4'hf),
407         .m6_cyc_i(ethernettxbus_cyc),
408         .m6_stb_i(ethernettxbus_stb),
409         .m6_ack_o(ethernettxbus_ack),
410
411         // Slave 0
412         .s0_dat_i(norflash_dat_r),
413         .s0_adr_o(norflash_adr),
414         .s0_cyc_o(norflash_cyc),
415         .s0_stb_o(norflash_stb),
416         .s0_ack_i(norflash_ack),
417         // Slave 1
418         .s1_dat_i(32'bx),
419         .s1_dat_o(),
420         .s1_adr_o(),
421         .s1_cti_o(),
422         .s1_sel_o(),
423         .s1_we_o(),
424         .s1_cyc_o(),
425         .s1_stb_o(),
426         .s1_ack_i(1'b0),
427         // Slave 2
428         .s2_dat_i(brg_dat_r),
429         .s2_dat_o(brg_dat_w),
430         .s2_adr_o(brg_adr),
431         .s2_cti_o(brg_cti),
432         .s2_sel_o(brg_sel),
433         .s2_we_o(brg_we),
434         .s2_cyc_o(brg_cyc),
435         .s2_stb_o(brg_stb),
436         .s2_ack_i(brg_ack),
437         // Slave 3
438         .s3_dat_i(csrbrg_dat_r),
439         .s3_dat_o(csrbrg_dat_w),
440         .s3_adr_o(csrbrg_adr),
441         .s3_we_o(csrbrg_we),
442         .s3_cyc_o(csrbrg_cyc),
443         .s3_stb_o(csrbrg_stb),
444         .s3_ack_i(csrbrg_ack),
445         // Slave 4
446         .s4_dat_i(32'bx),
447         .s4_dat_o(),
448         .s4_adr_o(),
449         .s4_we_o(),
450         .s4_cyc_o(),
451         .s4_stb_o(),
452         .s4_ack_i(1'b0)
453 );
454
455 //------------------------------------------------------------------
456 // CSR bus
457 //------------------------------------------------------------------
458 wire [13:0]     csr_a;
459 wire            csr_we;
460 wire [31:0]     csr_dw;
461 wire [31:0]     csr_dr_uart,
462                 csr_dr_sysctl,
463                 csr_dr_hpdmc,
464                 csr_dr_vga,
465                 csr_dr_ac97,
466                 csr_dr_pfpu,
467                 csr_dr_tmu,
468                 csr_dr_ethernet,
469                 csr_dr_fmlmeter,
470                 csr_dr_videoin;
471
472 //------------------------------------------------------------------
473 // FML master wires
474 //------------------------------------------------------------------
475 wire [`SDRAM_DEPTH-1:0] fml_brg_adr,
476                         fml_vga_adr,
477                         fml_tmur_adr,
478                         fml_tmudr_adr,
479                         fml_tmuw_adr,
480                         fml_videoin_adr;
481
482 wire                    fml_brg_stb,
483                         fml_vga_stb,
484                         fml_tmur_stb,
485                         fml_tmudr_stb,
486                         fml_tmuw_stb,
487                         fml_videoin_stb;
488
489 wire                    fml_brg_we;
490
491 wire                    fml_brg_ack,
492                         fml_vga_ack,
493                         fml_tmur_ack,
494                         fml_tmudr_ack,
495                         fml_tmuw_ack,
496                         fml_videoin_ack;
497
498 wire [7:0]              fml_brg_sel,
499                         fml_tmuw_sel;
500
501 wire [63:0]             fml_brg_dw,
502                         fml_tmuw_dw,
503                         fml_videoin_dw;
504
505 wire [63:0]             fml_brg_dr,
506                         fml_vga_dr,
507                         fml_tmur_dr,
508                         fml_tmudr_dr;
509
510 //------------------------------------------------------------------
511 // FML slave wires, to memory controller
512 //------------------------------------------------------------------
513 wire [`SDRAM_DEPTH-1:0] fml_adr;
514 wire fml_stb;
515 wire fml_we;
516 wire fml_ack;
517 wire [7:0] fml_sel;
518 wire [63:0] fml_dw;
519 wire [63:0] fml_dr;
520
521 //---------------------------------------------------------------------------
522 // FML arbiter
523 //---------------------------------------------------------------------------
524 fmlarb #(
525         .fml_depth(`SDRAM_DEPTH)
526 ) fmlarb (
527         .sys_clk(sys_clk),
528         .sys_rst(sys_rst),
529
530         /* VGA framebuffer (high priority) */
531         .m0_adr(fml_vga_adr),
532         .m0_stb(fml_vga_stb),
533         .m0_we(1'b0),
534         .m0_ack(fml_vga_ack),
535         .m0_sel(8'bx),
536         .m0_di(64'bx),
537         .m0_do(fml_vga_dr),
538
539         /* WISHBONE bridge */
540         .m1_adr(fml_brg_adr),
541         .m1_stb(fml_brg_stb),
542         .m1_we(fml_brg_we),
543         .m1_ack(fml_brg_ack),
544         .m1_sel(fml_brg_sel),
545         .m1_di(fml_brg_dw),
546         .m1_do(fml_brg_dr),
547
548         /* TMU, pixel read DMA (texture) */
549         .m2_adr(fml_tmur_adr),
550         .m2_stb(fml_tmur_stb),
551         .m2_we(1'b0),
552         .m2_ack(fml_tmur_ack),
553         .m2_sel(8'bx),
554         .m2_di(64'bx),
555         .m2_do(fml_tmur_dr),
556
557         /* TMU, pixel write DMA */
558         .m3_adr(fml_tmuw_adr),
559         .m3_stb(fml_tmuw_stb),
560         .m3_we(1'b1),
561         .m3_ack(fml_tmuw_ack),
562         .m3_sel(fml_tmuw_sel),
563         .m3_di(fml_tmuw_dw),
564         .m3_do(),
565
566         /* TMU, pixel read DMA (destination) */
567         .m4_adr(fml_tmudr_adr),
568         .m4_stb(fml_tmudr_stb),
569         .m4_we(1'b0),
570         .m4_ack(fml_tmudr_ack),
571         .m4_sel(8'bx),
572         .m4_di(64'bx),
573         .m4_do(fml_tmudr_dr),
574
575         /* Video in */
576         .m5_adr(fml_videoin_adr),
577         .m5_stb(fml_videoin_stb),
578         .m5_we(1'b1),
579         .m5_ack(fml_videoin_ack),
580         .m5_sel(8'hff),
581         .m5_di(fml_videoin_dw),
582         .m5_do(),
583
584         .s_adr(fml_adr),
585         .s_stb(fml_stb),
586         .s_we(fml_we),
587         .s_ack(fml_ack),
588         .s_sel(fml_sel),
589         .s_di(fml_dr),
590         .s_do(fml_dw)
591 );
592
593 //---------------------------------------------------------------------------
594 // WISHBONE to CSR bridge
595 //---------------------------------------------------------------------------
596 csrbrg csrbrg(
597         .sys_clk(sys_clk),
598         .sys_rst(sys_rst),
599         
600         .wb_adr_i(csrbrg_adr),
601         .wb_dat_i(csrbrg_dat_w),
602         .wb_dat_o(csrbrg_dat_r),
603         .wb_cyc_i(csrbrg_cyc),
604         .wb_stb_i(csrbrg_stb),
605         .wb_we_i(csrbrg_we),
606         .wb_ack_o(csrbrg_ack),
607         
608         .csr_a(csr_a),
609         .csr_we(csr_we),
610         .csr_do(csr_dw),
611         /* combine all slave->master data lines with an OR */
612         .csr_di(
613                  csr_dr_uart
614                 |csr_dr_sysctl
615                 |csr_dr_hpdmc
616                 |csr_dr_vga
617                 |csr_dr_ac97
618                 |csr_dr_pfpu
619                 |csr_dr_tmu
620                 |csr_dr_ethernet
621                 |csr_dr_fmlmeter
622                 |csr_dr_videoin
623         )
624 );
625
626 //---------------------------------------------------------------------------
627 // WISHBONE to FML bridge
628 //---------------------------------------------------------------------------
629 wire dcb_stb;
630 wire [`SDRAM_DEPTH-1:0] dcb_adr;
631 wire [63:0] dcb_dat;
632 wire dcb_hit;
633
634 fmlbrg #(
635         .fml_depth(`SDRAM_DEPTH)
636 ) fmlbrg (
637         .sys_clk(sys_clk),
638         .sys_rst(sys_rst),
639         
640         .wb_adr_i(brg_adr),
641         .wb_cti_i(brg_cti),
642         .wb_dat_o(brg_dat_r),
643         .wb_dat_i(brg_dat_w),
644         .wb_sel_i(brg_sel),
645         .wb_stb_i(brg_stb),
646         .wb_cyc_i(brg_cyc),
647         .wb_ack_o(brg_ack),
648         .wb_we_i(brg_we),
649         
650         .fml_adr(fml_brg_adr),
651         .fml_stb(fml_brg_stb),
652         .fml_we(fml_brg_we),
653         .fml_ack(fml_brg_ack),
654         .fml_sel(fml_brg_sel),
655         .fml_di(fml_brg_dr),
656         .fml_do(fml_brg_dw),
657
658         .dcb_stb(dcb_stb),
659         .dcb_adr(dcb_adr),
660         .dcb_dat(dcb_dat),
661         .dcb_hit(dcb_hit)
662 );
663
664 //---------------------------------------------------------------------------
665 // Interrupts
666 //---------------------------------------------------------------------------
667 wire gpio_irq;
668 wire timer0_irq;
669 wire timer1_irq;
670 wire uartrx_irq;
671 wire uarttx_irq;
672 wire ac97crrequest_irq;
673 wire ac97crreply_irq;
674 wire ac97dmar_irq;
675 wire ac97dmaw_irq;
676 wire pfpu_irq;
677 wire tmu_irq;
678 wire ethernetrx_irq;
679 wire ethernettx_irq;
680 wire videoin_irq;
681
682 wire [31:0] cpu_interrupt;
683 assign cpu_interrupt = {18'd0,
684         videoin_irq,
685         ethernettx_irq,
686         ethernetrx_irq,
687         tmu_irq,
688         pfpu_irq,
689         ac97dmaw_irq,
690         ac97dmar_irq,
691         ac97crreply_irq,
692         ac97crrequest_irq,
693         uarttx_irq,
694         uartrx_irq,
695         timer1_irq,
696         timer0_irq,
697         gpio_irq
698 };
699
700 //---------------------------------------------------------------------------
701 // LM32 CPU
702 //---------------------------------------------------------------------------
703 lm32_top cpu(
704         .clk_i(sys_clk),
705         .rst_i(sys_rst),
706         .interrupt(cpu_interrupt),
707
708         .I_ADR_O(cpuibus_adr),
709         .I_DAT_I(cpuibus_dat_r),
710         .I_DAT_O(),
711         .I_SEL_O(),
712         .I_CYC_O(cpuibus_cyc),
713         .I_STB_O(cpuibus_stb),
714         .I_ACK_I(cpuibus_ack),
715         .I_WE_O(),
716         .I_CTI_O(cpuibus_cti),
717         .I_LOCK_O(),
718         .I_BTE_O(),
719         .I_ERR_I(1'b0),
720         .I_RTY_I(1'b0),
721
722         .D_ADR_O(cpudbus_adr),
723         .D_DAT_I(cpudbus_dat_r),
724         .D_DAT_O(cpudbus_dat_w),
725         .D_SEL_O(cpudbus_sel),
726         .D_CYC_O(cpudbus_cyc),
727         .D_STB_O(cpudbus_stb),
728         .D_ACK_I(cpudbus_ack),
729         .D_WE_O (cpudbus_we),
730         .D_CTI_O(cpudbus_cti),
731         .D_LOCK_O(),
732         .D_BTE_O(),
733         .D_ERR_I(1'b0),
734         .D_RTY_I(1'b0)
735 );
736
737 //---------------------------------------------------------------------------
738 // Boot ROM
739 //---------------------------------------------------------------------------
740 norflash16 #(
741         .adr_width(24)
742 ) norflash (
743         .sys_clk(sys_clk),
744         .sys_rst(sys_rst),
745
746         .wb_adr_i(norflash_adr),
747         .wb_dat_o(norflash_dat_r),
748         .wb_stb_i(norflash_stb),
749         .wb_cyc_i(norflash_cyc),
750         .wb_ack_o(norflash_ack),
751         
752         .flash_adr(flash_adr),
753         .flash_d(flash_d)
754 );
755
756 assign flash_oe_n = 1'b0;
757 assign flash_we_n = 1'b1;
758 assign flash_ce_n = 1'b0;
759
760 //---------------------------------------------------------------------------
761 // UART
762 //---------------------------------------------------------------------------
763 uart #(
764         .csr_addr(4'h0),
765         .clk_freq(`CLOCK_FREQUENCY),
766         .baud(`BAUD_RATE)
767 ) uart (
768         .sys_clk(sys_clk),
769         .sys_rst(sys_rst),
770
771         .csr_a(csr_a),
772         .csr_we(csr_we),
773         .csr_di(csr_dw),
774         .csr_do(csr_dr_uart),
775         
776         .rx_irq(uartrx_irq),
777         .tx_irq(uarttx_irq),
778         
779         .uart_rxd(uart_rx),
780         .uart_txd(uart_tx)
781 );
782
783 //---------------------------------------------------------------------------
784 // System Controller
785 //---------------------------------------------------------------------------
786 wire [13:0] gpio_outputs;
787 wire [31:0] capabilities;
788
789 sysctl #(
790         .csr_addr(4'h1),
791         .ninputs(3),
792         .noutputs(2),
793         .systemid(32'h4D4F4E45) /* MONE */
794 ) sysctl (
795         .sys_clk(sys_clk),
796         .sys_rst(sys_rst),
797
798         .gpio_irq(gpio_irq),
799         .timer0_irq(timer0_irq),
800         .timer1_irq(timer1_irq),
801
802         .csr_a(csr_a),
803         .csr_we(csr_we),
804         .csr_di(csr_dw),
805         .csr_do(csr_dr_sysctl),
806
807         .gpio_inputs({btn3, btn2, btn1}),
808         .gpio_outputs({led2, led1}),
809
810         .capabilities(capabilities),
811         .hard_reset(hard_reset)
812 );
813
814 gen_capabilities gen_capabilities(
815         .capabilities(capabilities)
816 );
817
818 //---------------------------------------------------------------------------
819 // DDR SDRAM
820 //---------------------------------------------------------------------------
821 ddram #(
822         .csr_addr(4'h2)
823 ) ddram (
824         .sys_clk(sys_clk),
825         .sys_clk_n(sys_clk_n),
826         .sys_rst(sys_rst),
827
828         .csr_a(csr_a),
829         .csr_we(csr_we),
830         .csr_di(csr_dw),
831         .csr_do(csr_dr_hpdmc),
832
833         .fml_adr(fml_adr),
834         .fml_stb(fml_stb),
835         .fml_we(fml_we),
836         .fml_ack(fml_ack),
837         .fml_sel(fml_sel),
838         .fml_di(fml_dw),
839         .fml_do(fml_dr),
840         
841         .sdram_clk_p(sdram_clk_p),
842         .sdram_clk_n(sdram_clk_n),
843         .sdram_cke(sdram_cke),
844         .sdram_cs_n(sdram_cs_n),
845         .sdram_we_n(sdram_we_n),
846         .sdram_cas_n(sdram_cas_n),
847         .sdram_ras_n(sdram_ras_n),
848         .sdram_dqm(sdram_dm),
849         .sdram_adr(sdram_adr),
850         .sdram_ba(sdram_ba),
851         .sdram_dq(sdram_dq),
852         .sdram_dqs(sdram_dqs)
853 );
854
855 //---------------------------------------------------------------------------
856 // VGA
857 //---------------------------------------------------------------------------
858 vga #(
859         .csr_addr(4'h3),
860         .fml_depth(`SDRAM_DEPTH)
861 ) vga (
862         .sys_clk(sys_clk),
863         .sys_rst(sys_rst),
864         
865         .csr_a(csr_a),
866         .csr_we(csr_we),
867         .csr_di(csr_dw),
868         .csr_do(csr_dr_vga),
869         
870         .fml_adr(fml_vga_adr),
871         .fml_stb(fml_vga_stb),
872         .fml_ack(fml_vga_ack),
873         .fml_di(fml_vga_dr),
874
875         .dcb_stb(dcb_stb),
876         .dcb_adr(dcb_adr),
877         .dcb_dat(dcb_dat),
878         .dcb_hit(dcb_hit),
879         
880         .vga_psave_n(vga_psave_n),
881         .vga_hsync_n(vga_hsync_n),
882         .vga_vsync_n(vga_vsync_n),
883         .vga_r(vga_r),
884         .vga_g(vga_g),
885         .vga_b(vga_b),
886         .vga_clk(vga_clk),
887
888         .vga_sda(vga_sda),
889         .vga_sdc(vga_sdc)
890 );
891
892 //---------------------------------------------------------------------------
893 // AC97
894 //---------------------------------------------------------------------------
895 `ifdef ENABLE_AC97
896 wire ac97_clk_b;
897 BUFG b_ac97(
898         .I(ac97_clk),
899         .O(ac97_clk_b)
900 );
901 ac97 #(
902         .csr_addr(4'h4)
903 ) ac97 (
904         .sys_clk(sys_clk),
905         .sys_rst(sys_rst),
906         .ac97_clk(ac97_clk_b),
907         .ac97_rst_n(ac97_rst_n),
908         
909         .ac97_sin(ac97_sin),
910         .ac97_sout(ac97_sout),
911         .ac97_sync(ac97_sync),
912         
913         .csr_a(csr_a),
914         .csr_we(csr_we),
915         .csr_di(csr_dw),
916         .csr_do(csr_dr_ac97),
917         
918         .crrequest_irq(ac97crrequest_irq),
919         .crreply_irq(ac97crreply_irq),
920         .dmar_irq(ac97dmar_irq),
921         .dmaw_irq(ac97dmaw_irq),
922         
923         .wbm_adr_o(ac97bus_adr),
924         .wbm_cti_o(ac97bus_cti),
925         .wbm_we_o(ac97bus_we),
926         .wbm_cyc_o(ac97bus_cyc),
927         .wbm_stb_o(ac97bus_stb),
928         .wbm_ack_i(ac97bus_ack),
929         .wbm_dat_i(ac97bus_dat_r),
930         .wbm_dat_o(ac97bus_dat_w)
931 );
932
933 `else
934 assign csr_dr_ac97 = 32'd0;
935
936 assign ac97crrequest_irq = 1'b0;
937 assign ac97crreply_irq = 1'b0;
938 assign ac97dmar_irq = 1'b0;
939 assign ac97dmaw_irq = 1'b0;
940
941 assign ac97_sout = 1'b0;
942 assign ac97_sync = 1'b0;
943
944 assign ac97bus_adr = 32'bx;
945 assign ac97bus_cti = 3'bx;
946 assign ac97bus_we = 1'bx;
947 assign ac97bus_cyc = 1'b0;
948 assign ac97bus_stb = 1'b0;
949 assign ac97bus_dat_w = 32'bx;
950 `endif
951
952 //---------------------------------------------------------------------------
953 // Programmable FPU
954 //---------------------------------------------------------------------------
955 `ifdef ENABLE_PFPU
956 pfpu #(
957         .csr_addr(4'h5)
958 ) pfpu (
959         .sys_clk(sys_clk),
960         .sys_rst(sys_rst),
961         
962         .csr_a(csr_a),
963         .csr_we(csr_we),
964         .csr_di(csr_dw),
965         .csr_do(csr_dr_pfpu),
966         
967         .irq(pfpu_irq),
968         
969         .wbm_dat_o(pfpubus_dat_w),
970         .wbm_adr_o(pfpubus_adr),
971         .wbm_cyc_o(pfpubus_cyc),
972         .wbm_stb_o(pfpubus_stb),
973         .wbm_ack_i(pfpubus_ack)
974 );
975
976 `else
977 assign csr_dr_pfpu = 32'd0;
978
979 assign pfpu_irq = 1'b0;
980
981 assign pfpubus_dat_w = 32'hx;
982 assign pfpubus_adr = 32'hx;
983 assign pfpubus_cyc = 1'b0;
984 assign pfpubus_stb = 1'b0;
985 `endif
986
987 //---------------------------------------------------------------------------
988 // Texture Mapping Unit
989 //---------------------------------------------------------------------------
990 `ifdef ENABLE_TMU
991 tmu2 #(
992         .csr_addr(4'h6),
993         .fml_depth(`SDRAM_DEPTH)
994 ) tmu (
995         .sys_clk(sys_clk),
996         .sys_rst(sys_rst),
997
998         .csr_a(csr_a),
999         .csr_we(csr_we),
1000         .csr_di(csr_dw),
1001         .csr_do(csr_dr_tmu),
1002
1003         .irq(tmu_irq),
1004
1005         .wbm_adr_o(tmumbus_adr),
1006         .wbm_cti_o(tmumbus_cti),
1007         .wbm_cyc_o(tmumbus_cyc),
1008         .wbm_stb_o(tmumbus_stb),
1009         .wbm_ack_i(tmumbus_ack),
1010         .wbm_dat_i(tmumbus_dat_r),
1011
1012         .fmlr_adr(fml_tmur_adr),
1013         .fmlr_stb(fml_tmur_stb),
1014         .fmlr_ack(fml_tmur_ack),
1015         .fmlr_di(fml_tmur_dr),
1016
1017         .fmldr_adr(fml_tmudr_adr),
1018         .fmldr_stb(fml_tmudr_stb),
1019         .fmldr_ack(fml_tmudr_ack),
1020         .fmldr_di(fml_tmudr_dr),
1021
1022         .fmlw_adr(fml_tmuw_adr),
1023         .fmlw_stb(fml_tmuw_stb),
1024         .fmlw_ack(fml_tmuw_ack),
1025         .fmlw_sel(fml_tmuw_sel),
1026         .fmlw_do(fml_tmuw_dw)
1027 );
1028
1029 `else
1030 assign csr_dr_tmu = 32'd0;
1031
1032 assign tmu_irq = 1'b0;
1033
1034 assign tmumbus_adr = 32'hx;
1035 assign tmumbus_cti = 3'bxxx;
1036 assign tmumbus_cyc = 1'b0;
1037 assign tmumbus_stb = 1'b0;
1038
1039 assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
1040 assign fml_tmur_stb = 1'b0;
1041
1042 assign fml_tmudr_adr = {`SDRAM_DEPTH{1'bx}};
1043 assign fml_tmudr_stb = 1'b0;
1044
1045 assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
1046 assign fml_tmuw_stb = 1'b0;
1047 assign fml_tmuw_sel = 8'bx;
1048 assign fml_tmuw_dw = 64'bx;
1049 `endif
1050
1051 //---------------------------------------------------------------------------
1052 // Ethernet
1053 //---------------------------------------------------------------------------
1054 `ifdef ENABLE_ETHERNET
1055 wire phy_tx_clk_b0;
1056 wire phy_tx_clk_b;
1057 BUFIO2 b_phy_tx_clk0(
1058         .I(phy_tx_clk),
1059         .DIVCLK(phy_tx_clk_b0)
1060 );
1061 BUFG b_phy_tx_clk(
1062         .I(phy_tx_clk_b0),
1063         .O(phy_tx_clk_b)
1064 );
1065 wire phy_rx_clk_b0;
1066 wire phy_rx_clk_b;
1067 BUFIO2 b_phy_rx_clk0(
1068         .I(phy_rx_clk),
1069         .DIVCLK(phy_rx_clk_b0)
1070 );
1071 BUFG b_phy_rx_clk(
1072         .I(phy_rx_clk_b0),
1073         .O(phy_rx_clk_b)
1074 );
1075 minimac #(
1076         .csr_addr(4'h9)
1077 ) ethernet (
1078         .sys_clk(sys_clk),
1079         .sys_rst(sys_rst),
1080
1081         .csr_a(csr_a),
1082         .csr_we(csr_we),
1083         .csr_di(csr_dw),
1084         .csr_do(csr_dr_ethernet),
1085
1086         .wbrx_adr_o(ethernetrxbus_adr),
1087         .wbrx_cti_o(ethernetrxbus_cti),
1088         .wbrx_cyc_o(ethernetrxbus_cyc),
1089         .wbrx_stb_o(ethernetrxbus_stb),
1090         .wbrx_ack_i(ethernetrxbus_ack),
1091         .wbrx_dat_o(ethernetrxbus_dat_w),
1092
1093         .wbtx_adr_o(ethernettxbus_adr),
1094         .wbtx_cti_o(ethernettxbus_cti),
1095         .wbtx_cyc_o(ethernettxbus_cyc),
1096         .wbtx_stb_o(ethernettxbus_stb),
1097         .wbtx_ack_i(ethernettxbus_ack),
1098         .wbtx_dat_i(ethernettxbus_dat_r),
1099
1100         .irq_rx(ethernetrx_irq),
1101         .irq_tx(ethernettx_irq),
1102
1103         .phy_tx_clk(phy_tx_clk_b),
1104         .phy_tx_data(phy_tx_data),
1105         .phy_tx_en(phy_tx_en),
1106         .phy_tx_er(phy_tx_er),
1107         .phy_rx_clk(phy_rx_clk_b),
1108         .phy_rx_data(phy_rx_data),
1109         .phy_dv(phy_dv),
1110         .phy_rx_er(phy_rx_er),
1111         .phy_col(phy_col),
1112         .phy_crs(phy_crs),
1113         .phy_mii_clk(phy_mii_clk),
1114         .phy_mii_data(phy_mii_data)
1115 );
1116 `else
1117 assign csr_dr_ethernet = 32'd0;
1118 assign ethernetrxbus_adr = 32'bx;
1119 assign ethernetrxbus_cti = 3'bx;
1120 assign ethernetrxbus_cyc = 1'b0;
1121 assign ethernetrxbus_stb = 1'b0;
1122 assign ethernetrxbus_dat_w = 32'bx;
1123 assign ethernettxbus_adr = 32'bx;
1124 assign ethernettxbus_cti = 3'bx;
1125 assign ethernettxbus_cyc = 1'b0;
1126 assign ethernettxbus_stb = 1'b0;
1127 assign ethernettxbus_dat_r = 32'bx;
1128 assign ethernetrx_irq = 1'b0;
1129 assign ethernettx_irq = 1'b0;
1130 assign phy_tx_data = 4'b0;
1131 assign phy_tx_en = 1'b0;
1132 assign phy_tx_er = 1'b0;
1133 assign phy_mii_clk = 1'b0;
1134 assign phy_mii_data = 1'bz;
1135 `endif
1136
1137 always @(posedge clk50) phy_clk <= ~phy_clk;
1138
1139 //---------------------------------------------------------------------------
1140 // FastMemoryLink usage and performance meter
1141 //---------------------------------------------------------------------------
1142 `ifdef ENABLE_FMLMETER
1143 fmlmeter #(
1144         .csr_addr(4'ha)
1145 ) fmlmeter (
1146         .sys_clk(sys_clk),
1147         .sys_rst(sys_rst),
1148
1149         .csr_a(csr_a),
1150         .csr_we(csr_we),
1151         .csr_di(csr_dw),
1152         .csr_do(csr_dr_fmlmeter),
1153
1154         .fml_stb(fml_stb),
1155         .fml_ack(fml_ack)
1156 );
1157 `else
1158 assign csr_dr_fmlmeter = 32'd0;
1159 `endif
1160
1161 //---------------------------------------------------------------------------
1162 // Video Input
1163 //---------------------------------------------------------------------------
1164 `ifdef ENABLE_VIDEOIN
1165 bt656cap #(
1166         .csr_addr(4'hb),
1167         .fml_depth(`SDRAM_DEPTH)
1168 ) videoin (
1169         .sys_clk(sys_clk),
1170         .sys_rst(sys_rst),
1171
1172         .csr_a(csr_a),
1173         .csr_we(csr_we),
1174         .csr_di(csr_dw),
1175         .csr_do(csr_dr_videoin),
1176
1177         .irq(videoin_irq),
1178
1179         .fml_adr(fml_videoin_adr),
1180         .fml_stb(fml_videoin_stb),
1181         .fml_ack(fml_videoin_ack),
1182         .fml_do(fml_videoin_dw),
1183
1184         .vid_clk(videoin_llc),
1185         .p(videoin_p),
1186         .sda(videoin_sda),
1187         .sdc(videoin_sdc)
1188 );
1189 `else
1190 assign csr_dr_videoin = 32'd0;
1191 assign videoin_irq = 1'b0;
1192
1193 assign fml_videoin_adr = {`SDRAM_DEPTH{1'bx}};
1194 assign fml_videoin_stb = 1'b0;
1195 assign fml_videoin_dw = 64'bx;
1196
1197 assign videoin_sda = 1'bz;
1198 assign videoin_sdc = 1'b0;
1199 `endif
1200
1201 // TODO
1202 assign mc_d[3:0] = 4'bz;
1203 assign mc_cmd = 1'bz;
1204 assign mc_clk = 1'b0;
1205
1206 assign usba_spd = 1'b0;
1207 assign usba_oe_n = 1'b0;
1208 assign usba_vp = 1'bz;
1209 assign usba_vm = 1'bz;
1210 assign usbb_spd = 1'b0;
1211 assign usbb_oe_n = 1'b0;
1212 assign usbb_vp = 1'bz;
1213 assign usbb_vm = 1'bz;
1214
1215 assign midi_tx = 1'b0;
1216
1217 assign dmxa_de = 1'b0;
1218 assign dmxa_d = 1'b0;
1219 assign dmxb_de = 1'b0;
1220 assign dmxb_d = 1'b0;
1221
1222 endmodule