540df04d9758ce040f83d28eb464e94c247d06f3
[mw/milkymist.git] / boards / milkymist-one / rtl / system.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module system(
21         input clkin,
22         input resetin,
23         
24         // Boot ROM
25         output [20:0] flash_adr,
26         input [7:0] flash_d,
27         output flash_byte_n,
28         output flash_oe_n,
29         output flash_we_n,
30         output flash_ce,
31         output flash_ac97_reset_n,
32
33         // UART
34         input uart_rxd,
35         output uart_txd,
36
37         // SD card
38         // TODO
39
40         // DDR SDRAM
41         output sdram_clk_p,
42         output sdram_clk_n,
43         output sdram_cke,
44         output sdram_cs_n,
45         output sdram_we_n,
46         output sdram_cas_n,
47         output sdram_ras_n,
48         output [3:0] sdram_dqm,
49         output [12:0] sdram_adr,
50         output [1:0] sdram_ba,
51         inout [31:0] sdram_dq,
52         inout [3:0] sdram_dqs,
53         
54         // GPIO
55         output [3:0] led,    // 2 GPIO OUT (2 LEDs for UART activity)
56         input [3:0] dipsw,   // 4 GPIO IN
57
58         // VGA
59         output vga_psave_n,
60         output vga_hsync_n,
61         output vga_vsync_n,
62         output vga_sync_n,
63         output vga_blank_n,
64         output [7:0] vga_r,
65         output [7:0] vga_g,
66         output [7:0] vga_b,
67         output vga_clkout,
68         
69         // AC97
70         input ac97_clk,
71         input ac97_sin,
72         output ac97_sout,
73         output ac97_sync
74
75         // TODO
76         // ISP1362
77
78         // Ethernet
79
80         // Video Input
81
82         // DMX512
83
84         // MIDI
85
86         // IR
87 );
88
89 //------------------------------------------------------------------
90 // Clock and Reset Generation
91 //------------------------------------------------------------------
92 wire sys_clk;
93 wire sys_clk_n;
94 wire hard_reset;
95
96 `ifndef SIMULATION
97 wire sys_clk_dcm;
98 wire sys_clk_n_dcm;
99
100 DCM_SP #(
101         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
102
103         .CLKFX_DIVIDE(3),               // 1 to 32
104         .CLKFX_MULTIPLY(2),             // 2 to 32
105
106         .CLKIN_DIVIDE_BY_2("FALSE"),
107         .CLKIN_PERIOD(`CLOCK_PERIOD),
108         .CLKOUT_PHASE_SHIFT("NONE"),
109         .CLK_FEEDBACK("1X"),
110         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
111         .DFS_FREQUENCY_MODE("LOW"),
112         .DLL_FREQUENCY_MODE("LOW"),
113         .DUTY_CYCLE_CORRECTION("TRUE"),
114         .PHASE_SHIFT(0),
115         .STARTUP_WAIT("TRUE")
116 ) clkgen_sys (
117         .CLK0(sys_clk_dcm),
118         .CLK90(),
119         .CLK180(sys_clk_n_dcm),
120         .CLK270(),
121
122         .CLK2X(),
123         .CLK2X180(),
124
125         .CLKDV(),
126         .CLKFX(),
127         .CLKFX180(),
128         .LOCKED(),
129         .CLKFB(sys_clk),
130         .CLKIN(clkin),
131         .RST(1'b0),
132         .PSEN(1'b0)
133 );
134 AUTOBUF b1(
135         .I(sys_clk_dcm),
136         .O(sys_clk)
137 );
138 AUTOBUF b2(
139         .I(sys_clk_n_dcm),
140         .O(sys_clk_n)
141 );
142 `else
143 assign sys_clk = clkin;
144 assign sys_clk_n = ~clkin;
145 `endif
146
147 `ifndef SIMULATION
148 /* Synchronize the reset input */
149 reg rst0;
150 reg rst1;
151 always @(posedge sys_clk) rst0 <= resetin;
152 always @(posedge sys_clk) rst1 <= rst0;
153
154 /* Debounce it (counter holds reset for 10.49ms),
155  * and generate power-on reset.
156  */
157 reg [19:0] rst_debounce;
158 reg sys_rst;
159 initial rst_debounce <= 20'hFFFFF;
160 initial sys_rst <= 1'b1;
161 always @(posedge sys_clk) begin
162         if(rst1 | hard_reset)
163                 rst_debounce <= 20'hFFFFF;
164         else if(rst_debounce != 20'd0)
165                 rst_debounce <= rst_debounce - 20'd1;
166         sys_rst <= rst_debounce != 20'd0;
167 end
168
169 /*
170  * We must release the Flash reset before the system reset
171  * because the Flash needs some time to come out of reset
172  * and the CPU begins fetching instructions from it
173  * as soon as the system reset is released.
174  * From datasheet, minimum reset pulse width is 100ns
175  * and reset-to-read time is 150ns.
176  * The reset is combined with the AC97 reset, which must be held for 1us.
177  * Here we use a 7-bit counter that holds reset
178  * for 1.28us and makes everybody happy.
179  */
180
181 reg [7:0] flash_rstcounter;
182 initial flash_rstcounter <= 8'd0;
183 always @(posedge sys_clk) begin
184         if(~rst1 & ~sys_rst) /* ~sys_rst is for debouncing */
185                 flash_rstcounter <= 8'd0;
186         else if(~flash_rstcounter[7])
187                 flash_rstcounter <= flash_rstcounter + 8'd1;
188 end
189
190 assign flash_ac97_reset_n = flash_rstcounter[7];
191
192 wire ac97_rst_n;
193 assign ac97_rst_n = flash_rstcounter[7];
194
195 `else
196 wire sys_rst;
197 assign sys_rst = ~resetin;
198 `endif
199
200 //------------------------------------------------------------------
201 // Wishbone master wires
202 //------------------------------------------------------------------
203 wire [31:0]     cpuibus_adr,
204                 cpudbus_adr,
205                 ac97bus_adr,
206                 pfpubus_adr,
207                 tmumbus_adr;
208
209 wire [2:0]      cpuibus_cti,
210                 cpudbus_cti,
211                 ac97bus_cti,
212                 tmumbus_cti;
213
214 wire [31:0]     cpuibus_dat_r,
215                 cpudbus_dat_r,
216                 cpudbus_dat_w,
217                 ac97bus_dat_r,
218                 ac97bus_dat_w,
219                 pfpubus_dat_w,
220                 tmumbus_dat_r;
221
222 wire [3:0]      cpudbus_sel;
223
224 wire            cpudbus_we,
225                 ac97bus_we;
226
227 wire            cpuibus_cyc,
228                 cpudbus_cyc,
229                 ac97bus_cyc,
230                 pfpubus_cyc,
231                 tmumbus_cyc;
232
233 wire            cpuibus_stb,
234                 cpudbus_stb,
235                 ac97bus_stb,
236                 pfpubus_stb,
237                 tmumbus_stb;
238
239 wire            cpuibus_ack,
240                 cpudbus_ack,
241                 ac97bus_ack,
242                 tmumbus_ack,
243                 pfpubus_ack;
244
245 //------------------------------------------------------------------
246 // Wishbone slave wires
247 //------------------------------------------------------------------
248 wire [31:0]     brg_adr,
249                 norflash_adr,
250                 csrbrg_adr;
251
252 wire [2:0]      brg_cti;
253
254 wire [31:0]     brg_dat_r,
255                 brg_dat_w,
256                 norflash_dat_r,
257                 csrbrg_dat_r,
258                 csrbrg_dat_w;
259
260 wire [3:0]      brg_sel;
261
262 wire            brg_we,
263                 csrbrg_we;
264
265 wire            brg_cyc,
266                 norflash_cyc,
267                 csrbrg_cyc;
268
269 wire            brg_stb,
270                 norflash_stb,
271                 csrbrg_stb;
272
273 wire            brg_ack,
274                 norflash_ack,
275                 csrbrg_ack;
276
277 //---------------------------------------------------------------------------
278 // Wishbone switch
279 //---------------------------------------------------------------------------
280 conbus #(
281         .s_addr_w(3),
282         .s0_addr(3'b000),       // norflash     0x00000000
283         .s1_addr(3'b001),       // free         0x20000000
284         .s2_addr(3'b010),       // FML bridge   0x40000000
285         .s3_addr(3'b100),       // CSR bridge   0x80000000
286         .s4_addr(3'b101)        // free         0xa0000000
287 ) conbus (
288         .sys_clk(sys_clk),
289         .sys_rst(sys_rst),
290
291         // Master 0
292         .m0_dat_i(32'hx),
293         .m0_dat_o(cpuibus_dat_r),
294         .m0_adr_i(cpuibus_adr),
295         .m0_cti_i(cpuibus_cti),
296         .m0_we_i(1'b0),
297         .m0_sel_i(4'hf),
298         .m0_cyc_i(cpuibus_cyc),
299         .m0_stb_i(cpuibus_stb),
300         .m0_ack_o(cpuibus_ack),
301         // Master 1
302         .m1_dat_i(cpudbus_dat_w),
303         .m1_dat_o(cpudbus_dat_r),
304         .m1_adr_i(cpudbus_adr),
305         .m1_cti_i(cpudbus_cti),
306         .m1_we_i(cpudbus_we),
307         .m1_sel_i(cpudbus_sel),
308         .m1_cyc_i(cpudbus_cyc),
309         .m1_stb_i(cpudbus_stb),
310         .m1_ack_o(cpudbus_ack),
311         // Master 2
312         .m2_dat_i(ac97bus_dat_w),
313         .m2_dat_o(ac97bus_dat_r),
314         .m2_adr_i(ac97bus_adr),
315         .m2_cti_i(ac97bus_cti),
316         .m2_we_i(ac97bus_we),
317         .m2_sel_i(4'hf),
318         .m2_cyc_i(ac97bus_cyc),
319         .m2_stb_i(ac97bus_stb),
320         .m2_ack_o(ac97bus_ack),
321         // Master 3
322         .m3_dat_i(pfpubus_dat_w),
323         .m3_dat_o(),
324         .m3_adr_i(pfpubus_adr),
325         .m3_cti_i(3'd0),
326         .m3_we_i(1'b1),
327         .m3_sel_i(4'hf),
328         .m3_cyc_i(pfpubus_cyc),
329         .m3_stb_i(pfpubus_stb),
330         .m3_ack_o(pfpubus_ack),
331         // Master 4
332         .m4_dat_i(32'bx),
333         .m4_dat_o(tmumbus_dat_r),
334         .m4_adr_i(tmumbus_adr),
335         .m4_cti_i(tmumbus_cti),
336         .m4_we_i(1'b0),
337         .m4_sel_i(4'hf),
338         .m4_cyc_i(tmumbus_cyc),
339         .m4_stb_i(tmumbus_stb),
340         .m4_ack_o(tmumbus_ack),
341
342         // Slave 0
343         .s0_dat_i(norflash_dat_r),
344         .s0_adr_o(norflash_adr),
345         .s0_cyc_o(norflash_cyc),
346         .s0_stb_o(norflash_stb),
347         .s0_ack_i(norflash_ack),
348         // Slave 1
349         .s1_dat_i(32'bx),
350         .s1_dat_o(),
351         .s1_adr_o(),
352         .s1_cti_o(),
353         .s1_sel_o(),
354         .s1_we_o(),
355         .s1_cyc_o(),
356         .s1_stb_o(),
357         .s1_ack_i(1'b0),
358         // Slave 2
359         .s2_dat_i(brg_dat_r),
360         .s2_dat_o(brg_dat_w),
361         .s2_adr_o(brg_adr),
362         .s2_cti_o(brg_cti),
363         .s2_sel_o(brg_sel),
364         .s2_we_o(brg_we),
365         .s2_cyc_o(brg_cyc),
366         .s2_stb_o(brg_stb),
367         .s2_ack_i(brg_ack),
368         // Slave 3
369         .s3_dat_i(csrbrg_dat_r),
370         .s3_dat_o(csrbrg_dat_w),
371         .s3_adr_o(csrbrg_adr),
372         .s3_we_o(csrbrg_we),
373         .s3_cyc_o(csrbrg_cyc),
374         .s3_stb_o(csrbrg_stb),
375         .s3_ack_i(csrbrg_ack),
376         // Slave 4
377         .s4_dat_i(32'bx),
378         .s4_dat_o(),
379         .s4_adr_o(),
380         .s4_we_o(),
381         .s4_cyc_o(),
382         .s4_stb_o(),
383         .s4_ack_i(1'b0)
384 );
385
386 //------------------------------------------------------------------
387 // CSR bus
388 //------------------------------------------------------------------
389 wire [13:0]     csr_a;
390 wire            csr_we;
391 wire [31:0]     csr_dw;
392 wire [31:0]     csr_dr_uart,
393                 csr_dr_sysctl,
394                 csr_dr_hpdmc,
395                 csr_dr_vga,
396                 csr_dr_ac97,
397                 csr_dr_pfpu,
398                 csr_dr_tmu;
399
400 //------------------------------------------------------------------
401 // FML master wires
402 //------------------------------------------------------------------
403 wire [`SDRAM_DEPTH-1:0] fml_brg_adr,
404                         fml_vga_adr,
405                         fml_tmur_adr,
406                         fml_tmuw_adr;
407
408 wire                    fml_brg_stb,
409                         fml_vga_stb,
410                         fml_tmur_stb,
411                         fml_tmuw_stb;
412
413 wire                    fml_brg_we;
414
415 wire                    fml_brg_ack,
416                         fml_vga_ack,
417                         fml_tmur_ack,
418                         fml_tmuw_ack;
419
420 wire [7:0]              fml_brg_sel,
421                         fml_tmuw_sel;
422
423 wire [63:0]             fml_brg_dw,
424                         fml_tmuw_dw;
425
426 wire [63:0]             fml_brg_dr,
427                         fml_vga_dr,
428                         fml_tmur_dr;
429
430 //------------------------------------------------------------------
431 // FML slave wires, to memory controller
432 //------------------------------------------------------------------
433 wire [`SDRAM_DEPTH-1:0] fml_adr;
434 wire fml_stb;
435 wire fml_we;
436 wire fml_ack;
437 wire [7:0] fml_sel;
438 wire [63:0] fml_dw;
439 wire [63:0] fml_dr;
440
441 //---------------------------------------------------------------------------
442 // FML arbiter
443 //---------------------------------------------------------------------------
444 fmlarb #(
445         .fml_depth(`SDRAM_DEPTH)
446 ) fmlarb (
447         .sys_clk(sys_clk),
448         .sys_rst(sys_rst),
449         
450         /* VGA framebuffer (high priority) */
451         .m0_adr(fml_vga_adr),
452         .m0_stb(fml_vga_stb),
453         .m0_we(1'b0),
454         .m0_ack(fml_vga_ack),
455         .m0_sel(8'bx),
456         .m0_di(64'bx),
457         .m0_do(fml_vga_dr),
458         
459         /* WISHBONE bridge */
460         .m1_adr(fml_brg_adr),
461         .m1_stb(fml_brg_stb),
462         .m1_we(fml_brg_we),
463         .m1_ack(fml_brg_ack),
464         .m1_sel(fml_brg_sel),
465         .m1_di(fml_brg_dw),
466         .m1_do(fml_brg_dr),
467         
468         /* TMU, pixel read DMA */
469         .m2_adr(fml_tmur_adr),
470         .m2_stb(fml_tmur_stb),
471         .m2_we(1'b0),
472         .m2_ack(fml_tmur_ack),
473         .m2_sel(8'bx),
474         .m2_di(64'bx),
475         .m2_do(fml_tmur_dr),
476         
477         /* TMU, pixel write DMA */
478         .m3_adr(fml_tmuw_adr),
479         .m3_stb(fml_tmuw_stb),
480         .m3_we(1'b1),
481         .m3_ack(fml_tmuw_ack),
482         .m3_sel(fml_tmuw_sel),
483         .m3_di(fml_tmuw_dw),
484         .m3_do(),
485         
486         .s_adr(fml_adr),
487         .s_stb(fml_stb),
488         .s_we(fml_we),
489         .s_ack(fml_ack),
490         .s_sel(fml_sel),
491         .s_di(fml_dr),
492         .s_do(fml_dw)
493 );
494
495 //---------------------------------------------------------------------------
496 // WISHBONE to CSR bridge
497 //---------------------------------------------------------------------------
498 csrbrg csrbrg(
499         .sys_clk(sys_clk),
500         .sys_rst(sys_rst),
501         
502         .wb_adr_i(csrbrg_adr),
503         .wb_dat_i(csrbrg_dat_w),
504         .wb_dat_o(csrbrg_dat_r),
505         .wb_cyc_i(csrbrg_cyc),
506         .wb_stb_i(csrbrg_stb),
507         .wb_we_i(csrbrg_we),
508         .wb_ack_o(csrbrg_ack),
509         
510         .csr_a(csr_a),
511         .csr_we(csr_we),
512         .csr_do(csr_dw),
513         /* combine all slave->master data lines with an OR */
514         .csr_di(
515                  csr_dr_uart
516                 |csr_dr_sysctl
517                 |csr_dr_hpdmc
518                 |csr_dr_vga
519                 |csr_dr_ac97
520                 |csr_dr_pfpu
521                 |csr_dr_tmu
522         )
523 );
524
525 //---------------------------------------------------------------------------
526 // WISHBONE to FML bridge
527 //---------------------------------------------------------------------------
528 fmlbrg #(
529         .fml_depth(`SDRAM_DEPTH)
530 ) fmlbrg (
531         .sys_clk(sys_clk),
532         .sys_rst(sys_rst),
533         
534         .wb_adr_i(brg_adr),
535         .wb_cti_i(brg_cti),
536         .wb_dat_o(brg_dat_r),
537         .wb_dat_i(brg_dat_w),
538         .wb_sel_i(brg_sel),
539         .wb_stb_i(brg_stb),
540         .wb_cyc_i(brg_cyc),
541         .wb_ack_o(brg_ack),
542         .wb_we_i(brg_we),
543         
544         .fml_adr(fml_brg_adr),
545         .fml_stb(fml_brg_stb),
546         .fml_we(fml_brg_we),
547         .fml_ack(fml_brg_ack),
548         .fml_sel(fml_brg_sel),
549         .fml_di(fml_brg_dr),
550         .fml_do(fml_brg_dw)
551 );
552
553 //---------------------------------------------------------------------------
554 // Interrupts
555 //---------------------------------------------------------------------------
556 wire gpio_irq;
557 wire timer0_irq;
558 wire timer1_irq;
559 wire uartrx_irq;
560 wire uarttx_irq;
561 wire ac97crrequest_irq;
562 wire ac97crreply_irq;
563 wire ac97dmar_irq;
564 wire ac97dmaw_irq;
565 wire pfpu_irq;
566 wire tmu_irq;
567
568 wire [31:0] cpu_interrupt;
569 assign cpu_interrupt = {21'd0,
570         tmu_irq,
571         pfpu_irq,
572         ac97dmaw_irq,
573         ac97dmar_irq,
574         ac97crreply_irq,
575         ac97crrequest_irq,
576         uarttx_irq,
577         uartrx_irq,
578         timer1_irq,
579         timer0_irq,
580         gpio_irq
581 };
582
583 //---------------------------------------------------------------------------
584 // LM32 CPU
585 //---------------------------------------------------------------------------
586 lm32_top cpu(
587         .clk_i(sys_clk),
588         .rst_i(sys_rst),
589         .interrupt(cpu_interrupt),
590
591         .I_ADR_O(cpuibus_adr),
592         .I_DAT_I(cpuibus_dat_r),
593         .I_DAT_O(),
594         .I_SEL_O(),
595         .I_CYC_O(cpuibus_cyc),
596         .I_STB_O(cpuibus_stb),
597         .I_ACK_I(cpuibus_ack),
598         .I_WE_O(),
599         .I_CTI_O(cpuibus_cti),
600         .I_LOCK_O(),
601         .I_BTE_O(),
602         .I_ERR_I(1'b0),
603         .I_RTY_I(1'b0),
604
605         .D_ADR_O(cpudbus_adr),
606         .D_DAT_I(cpudbus_dat_r),
607         .D_DAT_O(cpudbus_dat_w),
608         .D_SEL_O(cpudbus_sel),
609         .D_CYC_O(cpudbus_cyc),
610         .D_STB_O(cpudbus_stb),
611         .D_ACK_I(cpudbus_ack),
612         .D_WE_O (cpudbus_we),
613         .D_CTI_O(cpudbus_cti),
614         .D_LOCK_O(),
615         .D_BTE_O(),
616         .D_ERR_I(1'b0),
617         .D_RTY_I(1'b0)
618 );
619
620 //---------------------------------------------------------------------------
621 // Boot ROM
622 //---------------------------------------------------------------------------
623 norflash8 #(
624         .adr_width(21)
625 ) norflash (
626         .sys_clk(sys_clk),
627         .sys_rst(sys_rst),
628
629         .wb_adr_i(norflash_adr),
630         .wb_dat_o(norflash_dat_r),
631         .wb_stb_i(norflash_stb),
632         .wb_cyc_i(norflash_cyc),
633         .wb_ack_o(norflash_ack),
634         
635         .flash_adr(flash_adr),
636         .flash_d(flash_d)
637
638 );
639
640 assign flash_byte_n = 1'b0;
641 assign flash_oe_n = 1'b0;
642 assign flash_we_n = 1'b1;
643 assign flash_ce = 1'b1;
644
645 //---------------------------------------------------------------------------
646 // UART
647 //---------------------------------------------------------------------------
648 uart #(
649         .csr_addr(4'h0),
650         .clk_freq(`CLOCK_FREQUENCY),
651         .baud(`BAUD_RATE)
652 ) uart (
653         .sys_clk(sys_clk),
654         .sys_rst(sys_rst),
655
656         .csr_a(csr_a),
657         .csr_we(csr_we),
658         .csr_di(csr_dw),
659         .csr_do(csr_dr_uart),
660         
661         .rx_irq(uartrx_irq),
662         .tx_irq(uarttx_irq),
663         
664         .uart_rxd(uart_rxd),
665         .uart_txd(uart_txd)
666 );
667
668 /* LED0 and LED1 are used as TX/RX indicators.
669  * Generate long pulses so we have time to see them
670  */
671 reg [18:0] rxcounter;
672 reg rxled;
673 always @(posedge sys_clk) begin
674         if(~uart_rxd)
675                 rxcounter <= {19{1'b1}};
676         else if(rxcounter != 19'd0)
677                 rxcounter <= rxcounter - 19'd1;
678         rxled <= rxcounter != 19'd0;
679 end
680
681 reg [18:0] txcounter;
682 reg txled;
683 always @(posedge sys_clk) begin
684         if(~uart_txd)
685                 txcounter <= {19{1'b1}};
686         else if(txcounter != 19'd0)
687                 txcounter <= txcounter - 20'd1;
688         txled <= txcounter != 19'd0;
689 end
690
691 assign led[0] = txled;
692 assign led[1] = rxled;
693
694 //---------------------------------------------------------------------------
695 // System Controller
696 //---------------------------------------------------------------------------
697 wire [13:0] gpio_outputs;
698 wire [31:0] capabilities;
699
700 sysctl #(
701         .csr_addr(4'h1),
702         .ninputs(4),
703         .noutputs(2),
704         .systemid(32'h4D4F4E45) /* MONE */
705 ) sysctl (
706         .sys_clk(sys_clk),
707         .sys_rst(sys_rst),
708
709         .gpio_irq(gpio_irq),
710         .timer0_irq(timer0_irq),
711         .timer1_irq(timer1_irq),
712
713         .csr_a(csr_a),
714         .csr_we(csr_we),
715         .csr_di(csr_dw),
716         .csr_do(csr_dr_sysctl),
717
718         .gpio_inputs(dipsw),
719         .gpio_outputs(led[3:2]), /* LED0 and LED1 are used as TX/RX indicators. */
720
721         .capabilities(capabilities),
722         .hard_reset(hard_reset)
723 );
724
725 gen_capabilities gen_capabilities(
726         .capabilities(capabilities)
727 );
728
729 //---------------------------------------------------------------------------
730 // DDR SDRAM
731 //---------------------------------------------------------------------------
732 ddram #(
733         .csr_addr(4'h2)
734 ) ddram (
735         .sys_clk(sys_clk),
736         .sys_clk_n(sys_clk_n),
737         .sys_rst(sys_rst),
738
739         .csr_a(csr_a),
740         .csr_we(csr_we),
741         .csr_di(csr_dw),
742         .csr_do(csr_dr_hpdmc),
743
744         .fml_adr(fml_adr),
745         .fml_stb(fml_stb),
746         .fml_we(fml_we),
747         .fml_ack(fml_ack),
748         .fml_sel(fml_sel),
749         .fml_di(fml_dw),
750         .fml_do(fml_dr),
751         
752         .sdram_clk_p(sdram_clk_p),
753         .sdram_clk_n(sdram_clk_n),
754         .sdram_cke(sdram_cke),
755         .sdram_cs_n(sdram_cs_n),
756         .sdram_we_n(sdram_we_n),
757         .sdram_cas_n(sdram_cas_n),
758         .sdram_ras_n(sdram_ras_n),
759         .sdram_dqm(sdram_dqm),
760         .sdram_adr(sdram_adr),
761         .sdram_ba(sdram_ba),
762         .sdram_dq(sdram_dq),
763         .sdram_dqs(sdram_dqs)
764 );
765
766 //---------------------------------------------------------------------------
767 // VGA
768 //---------------------------------------------------------------------------
769 `ifdef ENABLE_VGA
770 vga #(
771         .csr_addr(4'h3),
772         .fml_depth(`SDRAM_DEPTH)
773 ) vga (
774         .sys_clk(sys_clk),
775         .sys_rst(sys_rst),
776         
777         .csr_a(csr_a),
778         .csr_we(csr_we),
779         .csr_di(csr_dw),
780         .csr_do(csr_dr_vga),
781         
782         .fml_adr(fml_vga_adr),
783         .fml_stb(fml_vga_stb),
784         .fml_ack(fml_vga_ack),
785         .fml_di(fml_vga_dr),
786         
787         .vga_psave_n(vga_psave_n),
788         .vga_hsync_n(vga_hsync_n),
789         .vga_vsync_n(vga_vsync_n),
790         .vga_sync_n(vga_sync_n),
791         .vga_blank_n(vga_blank_n),
792         .vga_r(vga_r),
793         .vga_g(vga_g),
794         .vga_b(vga_b),
795         .vga_clkout(vga_clkout)
796 );
797 `else
798 assign csr_dr_vga = 32'd0;
799 assign fml_vga_adr = {`SDRAM_DEPTH{1'bx}};
800 assign fml_vga_stb = 1'b0;
801 assign vga_psave_n = 1'b0;
802 assign vga_hsync_n = 1'b0;
803 assign vga_vsync_n = 1'b0;
804 assign vga_sync_n = 1'b0;
805 assign vga_blank_n = 1'b0;
806 assign vga_r = 8'd0;
807 assign vga_g = 8'd0;
808 assign vga_b = 8'd0;
809 assign vga_clkout = 1'b0;
810 `endif
811
812 //---------------------------------------------------------------------------
813 // AC97
814 //---------------------------------------------------------------------------
815 `ifdef ENABLE_AC97
816 wire ac97_clk_b;
817 AUTOBUF b_ac97(
818         .I(ac97_clk),
819         .O(ac97_clk_b)
820 );
821 ac97 #(
822         .csr_addr(4'h4)
823 ) ac97 (
824         .sys_clk(sys_clk),
825         .sys_rst(sys_rst),
826         .ac97_clk(ac97_clk_b),
827         .ac97_rst_n(ac97_rst_n),
828         
829         .ac97_sin(ac97_sin),
830         .ac97_sout(ac97_sout),
831         .ac97_sync(ac97_sync),
832         
833         .csr_a(csr_a),
834         .csr_we(csr_we),
835         .csr_di(csr_dw),
836         .csr_do(csr_dr_ac97),
837         
838         .crrequest_irq(ac97crrequest_irq),
839         .crreply_irq(ac97crreply_irq),
840         .dmar_irq(ac97dmar_irq),
841         .dmaw_irq(ac97dmaw_irq),
842         
843         .wbm_adr_o(ac97bus_adr),
844         .wbm_cti_o(ac97bus_cti),
845         .wbm_we_o(ac97bus_we),
846         .wbm_cyc_o(ac97bus_cyc),
847         .wbm_stb_o(ac97bus_stb),
848         .wbm_ack_i(ac97bus_ack),
849         .wbm_dat_i(ac97bus_dat_r),
850         .wbm_dat_o(ac97bus_dat_w)
851 );
852
853 `else
854 assign csr_dr_ac97 = 32'd0;
855
856 assign ac97crrequest_irq = 1'b0;
857 assign ac97crreply_irq = 1'b0;
858 assign ac97dmar_irq = 1'b0;
859 assign ac97dmaw_irq = 1'b0;
860
861 assign ac97_sout = 1'b0;
862 assign ac97_sync = 1'b0;
863
864 assign ac97bus_adr = 32'bx;
865 assign ac97bus_cti = 3'bx;
866 assign ac97bus_we = 1'bx;
867 assign ac97bus_cyc = 1'b0;
868 assign ac97bus_stb = 1'b0;
869 assign ac97bus_dat_w = 32'bx;
870 `endif
871
872 //---------------------------------------------------------------------------
873 // Programmable FPU
874 //---------------------------------------------------------------------------
875 `ifdef ENABLE_PFPU
876 pfpu #(
877         .csr_addr(4'h5)
878 ) pfpu (
879         .sys_clk(sys_clk),
880         .sys_rst(sys_rst),
881         
882         .csr_a(csr_a),
883         .csr_we(csr_we),
884         .csr_di(csr_dw),
885         .csr_do(csr_dr_pfpu),
886         
887         .irq(pfpu_irq),
888         
889         .wbm_dat_o(pfpubus_dat_w),
890         .wbm_adr_o(pfpubus_adr),
891         .wbm_cyc_o(pfpubus_cyc),
892         .wbm_stb_o(pfpubus_stb),
893         .wbm_ack_i(pfpubus_ack)
894 );
895
896 `else
897 assign csr_dr_pfpu = 32'd0;
898
899 assign pfpu_irq = 1'b0;
900
901 assign pfpubus_dat_w = 32'hx;
902 assign pfpubus_adr = 32'hx;
903 assign pfpubus_cyc = 1'b0;
904 assign pfpubus_stb = 1'b0;
905 `endif
906
907 //---------------------------------------------------------------------------
908 // Texture Mapping Unit
909 //---------------------------------------------------------------------------
910 `ifdef ENABLE_TMU
911 tmu #(
912         .csr_addr(4'h6),
913         .fml_depth(`SDRAM_DEPTH)
914 ) tmu (
915         .sys_clk(sys_clk),
916         .sys_rst(sys_rst),
917         
918         .csr_a(csr_a),
919         .csr_we(csr_we),
920         .csr_di(csr_dw),
921         .csr_do(csr_dr_tmu),
922         
923         .irq(tmu_irq),
924         
925         .wbm_adr_o(tmumbus_adr),
926         .wbm_cti_o(tmumbus_cti),
927         .wbm_cyc_o(tmumbus_cyc),
928         .wbm_stb_o(tmumbus_stb),
929         .wbm_ack_i(tmumbus_ack),
930         .wbm_dat_i(tmumbus_dat_r),
931         
932         .fmlr_adr(fml_tmur_adr),
933         .fmlr_stb(fml_tmur_stb),
934         .fmlr_ack(fml_tmur_ack),
935         .fmlr_di(fml_tmur_dr),
936         
937         .fmlw_adr(fml_tmuw_adr),
938         .fmlw_stb(fml_tmuw_stb),
939         .fmlw_ack(fml_tmuw_ack),
940         .fmlw_sel(fml_tmuw_sel),
941         .fmlw_do(fml_tmuw_dw)
942 );
943
944 `else
945 assign csr_dr_tmu = 32'd0;
946
947 assign tmu_irq = 1'b0;
948
949 assign tmumbus_adr = 32'hx;
950 assign tmumbus_cti = 3'bxxx;
951 assign tmumbus_cyc = 1'b0;
952 assign tmumbus_stb = 1'b0;
953
954 assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
955 assign fml_tmur_stb = 1'b0;
956
957 assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
958 assign fml_tmuw_stb = 1'b0;
959 assign fml_tmuw_sel = 8'bx;
960 assign fml_tmuw_dw = 64'bx;
961 `endif
962
963 endmodule