Basic bitstream synthesis OK for M1 except timing
[mw/milkymist.git] / boards / milkymist-one / rtl / system.v
1 /*
2  * Milkymist VJ SoC
3  * Copyright (C) 2007, 2008, 2009, 2010 Sebastien Bourdeauducq
4  *
5  * This program is free software: you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License as published by
7  * the Free Software Foundation, version 3 of the License.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  */
17
18 `include "setup.v"
19
20 module system(
21         input clk50,
22         
23         // Boot ROM
24         output [23:0] flash_adr,
25         input [15:0] flash_d,
26         output flash_oe_n,
27         output flash_we_n,
28         output flash_ce_n,
29         output flash_rst_n,
30         input flash_sts,
31
32         // UART
33         input uart_rx,
34         output uart_tx,
35
36         // GPIO
37         input btn1,
38         input btn2,
39         input btn3,
40         output led1,
41         output led2,
42
43         // DDR SDRAM
44         output sdram_clk_p,
45         output sdram_clk_n,
46         output sdram_cke,
47         output sdram_cs_n,
48         output sdram_we_n,
49         output sdram_cas_n,
50         output sdram_ras_n,
51         output [3:0] sdram_dm,
52         output [12:0] sdram_adr,
53         output [1:0] sdram_ba,
54         inout [31:0] sdram_dq,
55         inout [3:0] sdram_dqs,
56
57         // VGA
58         output vga_psave_n,
59         output vga_hsync_n,
60         output vga_vsync_n,
61         output [7:0] vga_r,
62         output [7:0] vga_g,
63         output [7:0] vga_b,
64         output vga_clk,
65         inout vga_sda,
66         output vga_sdc,
67
68         // Memory card
69         inout [3:0] mc_d,
70         inout mc_cmd,
71         output mc_clk,
72         
73         // AC97
74         input ac97_clk,
75         input ac97_sin,
76         output ac97_sout,
77         output ac97_sync,
78         output ac97_rst_n,
79
80         // USB
81         output usba_spd,
82         output usba_oe_n,
83         input usba_rcv,
84         inout usba_vp,
85         inout usba_vm,
86
87         output usbb_spd,
88         output usbb_oe_n,
89         input usbb_rcv,
90         inout usbb_vp,
91         inout usbb_vm,
92
93         // Ethernet
94         output phy_rst_n,
95         input phy_tx_clk,
96         output [3:0] phy_tx_data,
97         output phy_tx_en,
98         output phy_tx_er,
99         input phy_rx_clk,
100         input [3:0] phy_rx_data,
101         input phy_dv,
102         input phy_rx_er,
103         input phy_col,
104         input phy_crs,
105         input phy_irq_n,
106         output phy_mii_clk,
107         inout phy_mii_data,
108         output phy_clk,
109
110         // Video Input
111         input [7:0] videoin_p,
112         input videoin_hs,
113         input videoin_vs,
114         input videoin_field,
115         input videoin_llc,
116         input videoin_irq_n,
117         input videoin_rst_n,
118         inout videoin_sda,
119         output videoin_sdc,
120
121         // MIDI
122         output midi_tx,
123         input midi_rx,
124
125         // DMX512
126         input dmxa_r,
127         output dmxa_de,
128         output dmxa_d,
129         input dmxb_r,
130         output dmxb_de,
131         output dmxb_d,
132
133         // IR
134         input ir_rx,
135
136         // Expansion connector
137         input [11:0] exp
138 );
139
140 //------------------------------------------------------------------
141 // Clock and Reset Generation
142 //------------------------------------------------------------------
143 wire sys_clk;
144 wire sys_clk_n;
145 wire hard_reset;
146
147 `ifndef SIMULATION
148 wire sys_clk_dcm;
149 wire sys_clk_n_dcm;
150
151 DCM_SP #(
152         .CLKDV_DIVIDE(1.5),             // 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5
153
154         .CLKFX_DIVIDE(3),               // 1 to 32
155         .CLKFX_MULTIPLY(5),             // 2 to 32
156
157         .CLKIN_DIVIDE_BY_2("FALSE"),
158         .CLKIN_PERIOD(20.0),
159         .CLKOUT_PHASE_SHIFT("NONE"),
160         .CLK_FEEDBACK("NONE"),
161         .DESKEW_ADJUST("SYSTEM_SYNCHRONOUS"),
162         .DFS_FREQUENCY_MODE("LOW"),
163         .DLL_FREQUENCY_MODE("LOW"),
164         .DUTY_CYCLE_CORRECTION("TRUE"),
165         .PHASE_SHIFT(0),
166         .STARTUP_WAIT("TRUE")
167 ) clkgen_sys (
168         .CLK0(),
169         .CLK90(),
170         .CLK180(),
171         .CLK270(),
172
173         .CLK2X(),
174         .CLK2X180(),
175
176         .CLKDV(),
177         .CLKFX(sys_clk_dcm),
178         .CLKFX180(sys_clk_n_dcm),
179         .LOCKED(),
180         .CLKFB(),
181         .CLKIN(clk50),
182         .RST(1'b0),
183         .PSEN(1'b0)
184 );
185 AUTOBUF b1(
186         .I(sys_clk_dcm),
187         .O(sys_clk)
188 );
189 AUTOBUF b2(
190         .I(sys_clk_n_dcm),
191         .O(sys_clk_n)
192 );
193 `else
194 assign sys_clk = clkin;
195 assign sys_clk_n = ~clkin;
196 `endif
197
198 /* Debounce it (counter holds reset for 10.49ms),
199  * and generate power-on reset.
200  */
201 reg [19:0] rst_debounce;
202 reg sys_rst;
203 initial rst_debounce <= 20'hFFFFF;
204 initial sys_rst <= 1'b1;
205 always @(posedge sys_clk) begin
206         if(hard_reset)
207                 rst_debounce <= 20'hFFFFF;
208         else if(rst_debounce != 20'd0)
209                 rst_debounce <= rst_debounce - 20'd1;
210         sys_rst <= rst_debounce != 20'd0;
211 end
212
213 /*
214  * We must release the Flash reset before the system reset
215  * because the Flash needs some time to come out of reset
216  * and the CPU begins fetching instructions from it
217  * as soon as the system reset is released.
218  * From datasheet, minimum reset pulse width is 100ns
219  * and reset-to-read time is 150ns.
220  * The reset is combined with the AC97 reset, which must be held for 1us.
221  * Here we use a 7-bit counter that holds reset
222  * for 1.28us and makes everybody happy.
223  */
224
225 reg [7:0] flash_rstcounter;
226 initial flash_rstcounter <= 8'd0;
227 always @(posedge sys_clk) begin
228         if(hard_reset)
229                 flash_rstcounter <= 8'd0;
230         else if(~flash_rstcounter[7])
231                 flash_rstcounter <= flash_rstcounter + 8'd1;
232 end
233
234 assign flash_rst_n = flash_rstcounter[7];
235 assign ac97_rst_n = flash_rstcounter[7];
236 assign phy_rst_n = flash_rstcounter[7];
237
238 //------------------------------------------------------------------
239 // Wishbone master wires
240 //------------------------------------------------------------------
241 wire [31:0]     cpuibus_adr,
242                 cpudbus_adr,
243                 ac97bus_adr,
244                 pfpubus_adr,
245                 tmumbus_adr;
246
247 wire [2:0]      cpuibus_cti,
248                 cpudbus_cti,
249                 ac97bus_cti,
250                 tmumbus_cti;
251
252 wire [31:0]     cpuibus_dat_r,
253                 cpudbus_dat_r,
254                 cpudbus_dat_w,
255                 ac97bus_dat_r,
256                 ac97bus_dat_w,
257                 pfpubus_dat_w,
258                 tmumbus_dat_r;
259
260 wire [3:0]      cpudbus_sel;
261
262 wire            cpudbus_we,
263                 ac97bus_we;
264
265 wire            cpuibus_cyc,
266                 cpudbus_cyc,
267                 ac97bus_cyc,
268                 pfpubus_cyc,
269                 tmumbus_cyc;
270
271 wire            cpuibus_stb,
272                 cpudbus_stb,
273                 ac97bus_stb,
274                 pfpubus_stb,
275                 tmumbus_stb;
276
277 wire            cpuibus_ack,
278                 cpudbus_ack,
279                 ac97bus_ack,
280                 tmumbus_ack,
281                 pfpubus_ack;
282
283 //------------------------------------------------------------------
284 // Wishbone slave wires
285 //------------------------------------------------------------------
286 wire [31:0]     brg_adr,
287                 norflash_adr,
288                 csrbrg_adr;
289
290 wire [2:0]      brg_cti;
291
292 wire [31:0]     brg_dat_r,
293                 brg_dat_w,
294                 norflash_dat_r,
295                 csrbrg_dat_r,
296                 csrbrg_dat_w;
297
298 wire [3:0]      brg_sel;
299
300 wire            brg_we,
301                 csrbrg_we;
302
303 wire            brg_cyc,
304                 norflash_cyc,
305                 csrbrg_cyc;
306
307 wire            brg_stb,
308                 norflash_stb,
309                 csrbrg_stb;
310
311 wire            brg_ack,
312                 norflash_ack,
313                 csrbrg_ack;
314
315 //---------------------------------------------------------------------------
316 // Wishbone switch
317 //---------------------------------------------------------------------------
318 conbus #(
319         .s_addr_w(3),
320         .s0_addr(3'b000),       // norflash     0x00000000
321         .s1_addr(3'b001),       // free         0x20000000
322         .s2_addr(3'b010),       // FML bridge   0x40000000
323         .s3_addr(3'b100),       // CSR bridge   0x80000000
324         .s4_addr(3'b101)        // free         0xa0000000
325 ) conbus (
326         .sys_clk(sys_clk),
327         .sys_rst(sys_rst),
328
329         // Master 0
330         .m0_dat_i(32'hx),
331         .m0_dat_o(cpuibus_dat_r),
332         .m0_adr_i(cpuibus_adr),
333         .m0_cti_i(cpuibus_cti),
334         .m0_we_i(1'b0),
335         .m0_sel_i(4'hf),
336         .m0_cyc_i(cpuibus_cyc),
337         .m0_stb_i(cpuibus_stb),
338         .m0_ack_o(cpuibus_ack),
339         // Master 1
340         .m1_dat_i(cpudbus_dat_w),
341         .m1_dat_o(cpudbus_dat_r),
342         .m1_adr_i(cpudbus_adr),
343         .m1_cti_i(cpudbus_cti),
344         .m1_we_i(cpudbus_we),
345         .m1_sel_i(cpudbus_sel),
346         .m1_cyc_i(cpudbus_cyc),
347         .m1_stb_i(cpudbus_stb),
348         .m1_ack_o(cpudbus_ack),
349         // Master 2
350         .m2_dat_i(ac97bus_dat_w),
351         .m2_dat_o(ac97bus_dat_r),
352         .m2_adr_i(ac97bus_adr),
353         .m2_cti_i(ac97bus_cti),
354         .m2_we_i(ac97bus_we),
355         .m2_sel_i(4'hf),
356         .m2_cyc_i(ac97bus_cyc),
357         .m2_stb_i(ac97bus_stb),
358         .m2_ack_o(ac97bus_ack),
359         // Master 3
360         .m3_dat_i(pfpubus_dat_w),
361         .m3_dat_o(),
362         .m3_adr_i(pfpubus_adr),
363         .m3_cti_i(3'd0),
364         .m3_we_i(1'b1),
365         .m3_sel_i(4'hf),
366         .m3_cyc_i(pfpubus_cyc),
367         .m3_stb_i(pfpubus_stb),
368         .m3_ack_o(pfpubus_ack),
369         // Master 4
370         .m4_dat_i(32'bx),
371         .m4_dat_o(tmumbus_dat_r),
372         .m4_adr_i(tmumbus_adr),
373         .m4_cti_i(tmumbus_cti),
374         .m4_we_i(1'b0),
375         .m4_sel_i(4'hf),
376         .m4_cyc_i(tmumbus_cyc),
377         .m4_stb_i(tmumbus_stb),
378         .m4_ack_o(tmumbus_ack),
379
380         // Slave 0
381         .s0_dat_i(norflash_dat_r),
382         .s0_adr_o(norflash_adr),
383         .s0_cyc_o(norflash_cyc),
384         .s0_stb_o(norflash_stb),
385         .s0_ack_i(norflash_ack),
386         // Slave 1
387         .s1_dat_i(32'bx),
388         .s1_dat_o(),
389         .s1_adr_o(),
390         .s1_cti_o(),
391         .s1_sel_o(),
392         .s1_we_o(),
393         .s1_cyc_o(),
394         .s1_stb_o(),
395         .s1_ack_i(1'b0),
396         // Slave 2
397         .s2_dat_i(brg_dat_r),
398         .s2_dat_o(brg_dat_w),
399         .s2_adr_o(brg_adr),
400         .s2_cti_o(brg_cti),
401         .s2_sel_o(brg_sel),
402         .s2_we_o(brg_we),
403         .s2_cyc_o(brg_cyc),
404         .s2_stb_o(brg_stb),
405         .s2_ack_i(brg_ack),
406         // Slave 3
407         .s3_dat_i(csrbrg_dat_r),
408         .s3_dat_o(csrbrg_dat_w),
409         .s3_adr_o(csrbrg_adr),
410         .s3_we_o(csrbrg_we),
411         .s3_cyc_o(csrbrg_cyc),
412         .s3_stb_o(csrbrg_stb),
413         .s3_ack_i(csrbrg_ack),
414         // Slave 4
415         .s4_dat_i(32'bx),
416         .s4_dat_o(),
417         .s4_adr_o(),
418         .s4_we_o(),
419         .s4_cyc_o(),
420         .s4_stb_o(),
421         .s4_ack_i(1'b0)
422 );
423
424 //------------------------------------------------------------------
425 // CSR bus
426 //------------------------------------------------------------------
427 wire [13:0]     csr_a;
428 wire            csr_we;
429 wire [31:0]     csr_dw;
430 wire [31:0]     csr_dr_uart,
431                 csr_dr_sysctl,
432                 csr_dr_hpdmc,
433                 csr_dr_vga,
434                 csr_dr_ac97,
435                 csr_dr_pfpu,
436                 csr_dr_tmu,
437                 csr_dr_ethernet,
438                 csr_dr_fmlmeter;
439
440 //------------------------------------------------------------------
441 // FML master wires
442 //------------------------------------------------------------------
443 wire [`SDRAM_DEPTH-1:0] fml_brg_adr,
444                         fml_vga_adr,
445                         fml_tmur_adr,
446                         fml_tmudr_adr,
447                         fml_tmuw_adr;
448
449 wire                    fml_brg_stb,
450                         fml_vga_stb,
451                         fml_tmur_stb,
452                         fml_tmudr_stb,
453                         fml_tmuw_stb;
454
455 wire                    fml_brg_we;
456
457 wire                    fml_brg_ack,
458                         fml_vga_ack,
459                         fml_tmur_ack,
460                         fml_tmudr_ack,
461                         fml_tmuw_ack;
462
463 wire [7:0]              fml_brg_sel,
464                         fml_tmuw_sel;
465
466 wire [63:0]             fml_brg_dw,
467                         fml_tmuw_dw;
468
469 wire [63:0]             fml_brg_dr,
470                         fml_vga_dr,
471                         fml_tmur_dr,
472                         fml_tmudr_dr;
473
474 //------------------------------------------------------------------
475 // FML slave wires, to memory controller
476 //------------------------------------------------------------------
477 wire [`SDRAM_DEPTH-1:0] fml_adr;
478 wire fml_stb;
479 wire fml_we;
480 wire fml_ack;
481 wire [7:0] fml_sel;
482 wire [63:0] fml_dw;
483 wire [63:0] fml_dr;
484
485 //---------------------------------------------------------------------------
486 // FML arbiter
487 //---------------------------------------------------------------------------
488 fmlarb #(
489         .fml_depth(`SDRAM_DEPTH)
490 ) fmlarb (
491         .sys_clk(sys_clk),
492         .sys_rst(sys_rst),
493
494         /* VGA framebuffer (high priority) */
495         .m0_adr(fml_vga_adr),
496         .m0_stb(fml_vga_stb),
497         .m0_we(1'b0),
498         .m0_ack(fml_vga_ack),
499         .m0_sel(8'bx),
500         .m0_di(64'bx),
501         .m0_do(fml_vga_dr),
502
503         /* WISHBONE bridge */
504         .m1_adr(fml_brg_adr),
505         .m1_stb(fml_brg_stb),
506         .m1_we(fml_brg_we),
507         .m1_ack(fml_brg_ack),
508         .m1_sel(fml_brg_sel),
509         .m1_di(fml_brg_dw),
510         .m1_do(fml_brg_dr),
511
512         /* TMU, pixel read DMA (texture) */
513         .m2_adr(fml_tmur_adr),
514         .m2_stb(fml_tmur_stb),
515         .m2_we(1'b0),
516         .m2_ack(fml_tmur_ack),
517         .m2_sel(8'bx),
518         .m2_di(64'bx),
519         .m2_do(fml_tmur_dr),
520
521         /* TMU, pixel write DMA */
522         .m3_adr(fml_tmuw_adr),
523         .m3_stb(fml_tmuw_stb),
524         .m3_we(1'b1),
525         .m3_ack(fml_tmuw_ack),
526         .m3_sel(fml_tmuw_sel),
527         .m3_di(fml_tmuw_dw),
528         .m3_do(),
529
530         /* TMU, pixel read DMA (destination) */
531         .m4_adr(fml_tmudr_adr),
532         .m4_stb(fml_tmudr_stb),
533         .m4_we(1'b0),
534         .m4_ack(fml_tmudr_ack),
535         .m4_sel(8'bx),
536         .m4_di(64'bx),
537         .m4_do(fml_tmudr_dr),
538
539         .s_adr(fml_adr),
540         .s_stb(fml_stb),
541         .s_we(fml_we),
542         .s_ack(fml_ack),
543         .s_sel(fml_sel),
544         .s_di(fml_dr),
545         .s_do(fml_dw)
546 );
547
548 //---------------------------------------------------------------------------
549 // WISHBONE to CSR bridge
550 //---------------------------------------------------------------------------
551 csrbrg csrbrg(
552         .sys_clk(sys_clk),
553         .sys_rst(sys_rst),
554         
555         .wb_adr_i(csrbrg_adr),
556         .wb_dat_i(csrbrg_dat_w),
557         .wb_dat_o(csrbrg_dat_r),
558         .wb_cyc_i(csrbrg_cyc),
559         .wb_stb_i(csrbrg_stb),
560         .wb_we_i(csrbrg_we),
561         .wb_ack_o(csrbrg_ack),
562         
563         .csr_a(csr_a),
564         .csr_we(csr_we),
565         .csr_do(csr_dw),
566         /* combine all slave->master data lines with an OR */
567         .csr_di(
568                  csr_dr_uart
569                 |csr_dr_sysctl
570                 |csr_dr_hpdmc
571                 |csr_dr_vga
572                 |csr_dr_ac97
573                 |csr_dr_pfpu
574                 |csr_dr_tmu
575                 |csr_dr_ethernet
576                 |csr_dr_fmlmeter
577         )
578 );
579
580 //---------------------------------------------------------------------------
581 // WISHBONE to FML bridge
582 //---------------------------------------------------------------------------
583 fmlbrg #(
584         .fml_depth(`SDRAM_DEPTH)
585 ) fmlbrg (
586         .sys_clk(sys_clk),
587         .sys_rst(sys_rst),
588         
589         .wb_adr_i(brg_adr),
590         .wb_cti_i(brg_cti),
591         .wb_dat_o(brg_dat_r),
592         .wb_dat_i(brg_dat_w),
593         .wb_sel_i(brg_sel),
594         .wb_stb_i(brg_stb),
595         .wb_cyc_i(brg_cyc),
596         .wb_ack_o(brg_ack),
597         .wb_we_i(brg_we),
598         
599         .fml_adr(fml_brg_adr),
600         .fml_stb(fml_brg_stb),
601         .fml_we(fml_brg_we),
602         .fml_ack(fml_brg_ack),
603         .fml_sel(fml_brg_sel),
604         .fml_di(fml_brg_dr),
605         .fml_do(fml_brg_dw)
606 );
607
608 //---------------------------------------------------------------------------
609 // Interrupts
610 //---------------------------------------------------------------------------
611 wire gpio_irq;
612 wire timer0_irq;
613 wire timer1_irq;
614 wire uartrx_irq;
615 wire uarttx_irq;
616 wire ac97crrequest_irq;
617 wire ac97crreply_irq;
618 wire ac97dmar_irq;
619 wire ac97dmaw_irq;
620 wire pfpu_irq;
621 wire tmu_irq;
622
623 wire [31:0] cpu_interrupt;
624 assign cpu_interrupt = {21'd0,
625         tmu_irq,
626         pfpu_irq,
627         ac97dmaw_irq,
628         ac97dmar_irq,
629         ac97crreply_irq,
630         ac97crrequest_irq,
631         uarttx_irq,
632         uartrx_irq,
633         timer1_irq,
634         timer0_irq,
635         gpio_irq
636 };
637
638 //---------------------------------------------------------------------------
639 // LM32 CPU
640 //---------------------------------------------------------------------------
641 lm32_top cpu(
642         .clk_i(sys_clk),
643         .rst_i(sys_rst),
644         .interrupt(cpu_interrupt),
645
646         .I_ADR_O(cpuibus_adr),
647         .I_DAT_I(cpuibus_dat_r),
648         .I_DAT_O(),
649         .I_SEL_O(),
650         .I_CYC_O(cpuibus_cyc),
651         .I_STB_O(cpuibus_stb),
652         .I_ACK_I(cpuibus_ack),
653         .I_WE_O(),
654         .I_CTI_O(cpuibus_cti),
655         .I_LOCK_O(),
656         .I_BTE_O(),
657         .I_ERR_I(1'b0),
658         .I_RTY_I(1'b0),
659
660         .D_ADR_O(cpudbus_adr),
661         .D_DAT_I(cpudbus_dat_r),
662         .D_DAT_O(cpudbus_dat_w),
663         .D_SEL_O(cpudbus_sel),
664         .D_CYC_O(cpudbus_cyc),
665         .D_STB_O(cpudbus_stb),
666         .D_ACK_I(cpudbus_ack),
667         .D_WE_O (cpudbus_we),
668         .D_CTI_O(cpudbus_cti),
669         .D_LOCK_O(),
670         .D_BTE_O(),
671         .D_ERR_I(1'b0),
672         .D_RTY_I(1'b0)
673 );
674
675 //---------------------------------------------------------------------------
676 // Boot ROM
677 //---------------------------------------------------------------------------
678 norflash8 #(
679         .adr_width(24)
680 ) norflash (
681         .sys_clk(sys_clk),
682         .sys_rst(sys_rst),
683
684         .wb_adr_i(norflash_adr),
685         .wb_dat_o(norflash_dat_r),
686         .wb_stb_i(norflash_stb),
687         .wb_cyc_i(norflash_cyc),
688         .wb_ack_o(norflash_ack),
689         
690         .flash_adr(flash_adr),
691         .flash_d(flash_d)
692 );
693
694 assign flash_oe_n = 1'b0;
695 assign flash_we_n = 1'b1;
696 assign flash_ce_n = 1'b0;
697
698 //---------------------------------------------------------------------------
699 // UART
700 //---------------------------------------------------------------------------
701 uart #(
702         .csr_addr(4'h0),
703         .clk_freq(`CLOCK_FREQUENCY),
704         .baud(`BAUD_RATE)
705 ) uart (
706         .sys_clk(sys_clk),
707         .sys_rst(sys_rst),
708
709         .csr_a(csr_a),
710         .csr_we(csr_we),
711         .csr_di(csr_dw),
712         .csr_do(csr_dr_uart),
713         
714         .rx_irq(uartrx_irq),
715         .tx_irq(uarttx_irq),
716         
717         .uart_rxd(uart_rx),
718         .uart_txd(uart_tx)
719 );
720
721 //---------------------------------------------------------------------------
722 // System Controller
723 //---------------------------------------------------------------------------
724 wire [13:0] gpio_outputs;
725 wire [31:0] capabilities;
726
727 sysctl #(
728         .csr_addr(4'h1),
729         .ninputs(3),
730         .noutputs(2),
731         .systemid(32'h4D4F4E45) /* MONE */
732 ) sysctl (
733         .sys_clk(sys_clk),
734         .sys_rst(sys_rst),
735
736         .gpio_irq(gpio_irq),
737         .timer0_irq(timer0_irq),
738         .timer1_irq(timer1_irq),
739
740         .csr_a(csr_a),
741         .csr_we(csr_we),
742         .csr_di(csr_dw),
743         .csr_do(csr_dr_sysctl),
744
745         .gpio_inputs({btn3, btn2, btn1}),
746         .gpio_outputs({led2, led1}),
747
748         .capabilities(capabilities),
749         .hard_reset(hard_reset)
750 );
751
752 gen_capabilities gen_capabilities(
753         .capabilities(capabilities)
754 );
755
756 //---------------------------------------------------------------------------
757 // DDR SDRAM
758 //---------------------------------------------------------------------------
759 ddram #(
760         .csr_addr(4'h2)
761 ) ddram (
762         .sys_clk(sys_clk),
763         .sys_clk_n(sys_clk_n),
764         .sys_rst(sys_rst),
765
766         .csr_a(csr_a),
767         .csr_we(csr_we),
768         .csr_di(csr_dw),
769         .csr_do(csr_dr_hpdmc),
770
771         .fml_adr(fml_adr),
772         .fml_stb(fml_stb),
773         .fml_we(fml_we),
774         .fml_ack(fml_ack),
775         .fml_sel(fml_sel),
776         .fml_di(fml_dw),
777         .fml_do(fml_dr),
778         
779         .sdram_clk_p(sdram_clk_p),
780         .sdram_clk_n(sdram_clk_n),
781         .sdram_cke(sdram_cke),
782         .sdram_cs_n(sdram_cs_n),
783         .sdram_we_n(sdram_we_n),
784         .sdram_cas_n(sdram_cas_n),
785         .sdram_ras_n(sdram_ras_n),
786         .sdram_dqm(sdram_dm),
787         .sdram_adr(sdram_adr),
788         .sdram_ba(sdram_ba),
789         .sdram_dq(sdram_dq),
790         .sdram_dqs(sdram_dqs)
791 );
792
793 //---------------------------------------------------------------------------
794 // VGA
795 //---------------------------------------------------------------------------
796 vga #(
797         .csr_addr(4'h3),
798         .fml_depth(`SDRAM_DEPTH)
799 ) vga (
800         .sys_clk(sys_clk),
801         .sys_rst(sys_rst),
802         
803         .csr_a(csr_a),
804         .csr_we(csr_we),
805         .csr_di(csr_dw),
806         .csr_do(csr_dr_vga),
807         
808         .fml_adr(fml_vga_adr),
809         .fml_stb(fml_vga_stb),
810         .fml_ack(fml_vga_ack),
811         .fml_di(fml_vga_dr),
812         
813         .vga_psave_n(vga_psave_n),
814         .vga_hsync_n(vga_hsync_n),
815         .vga_vsync_n(vga_vsync_n),
816         .vga_r(vga_r),
817         .vga_g(vga_g),
818         .vga_b(vga_b),
819         .vga_clk(vga_clk)
820 );
821
822 //---------------------------------------------------------------------------
823 // AC97
824 //---------------------------------------------------------------------------
825 `ifdef ENABLE_AC97
826 wire ac97_clk_b;
827 AUTOBUF b_ac97(
828         .I(ac97_clk),
829         .O(ac97_clk_b)
830 );
831 ac97 #(
832         .csr_addr(4'h4)
833 ) ac97 (
834         .sys_clk(sys_clk),
835         .sys_rst(sys_rst),
836         .ac97_clk(ac97_clk_b),
837         .ac97_rst_n(ac97_rst_n),
838         
839         .ac97_sin(ac97_sin),
840         .ac97_sout(ac97_sout),
841         .ac97_sync(ac97_sync),
842         
843         .csr_a(csr_a),
844         .csr_we(csr_we),
845         .csr_di(csr_dw),
846         .csr_do(csr_dr_ac97),
847         
848         .crrequest_irq(ac97crrequest_irq),
849         .crreply_irq(ac97crreply_irq),
850         .dmar_irq(ac97dmar_irq),
851         .dmaw_irq(ac97dmaw_irq),
852         
853         .wbm_adr_o(ac97bus_adr),
854         .wbm_cti_o(ac97bus_cti),
855         .wbm_we_o(ac97bus_we),
856         .wbm_cyc_o(ac97bus_cyc),
857         .wbm_stb_o(ac97bus_stb),
858         .wbm_ack_i(ac97bus_ack),
859         .wbm_dat_i(ac97bus_dat_r),
860         .wbm_dat_o(ac97bus_dat_w)
861 );
862
863 `else
864 assign csr_dr_ac97 = 32'd0;
865
866 assign ac97crrequest_irq = 1'b0;
867 assign ac97crreply_irq = 1'b0;
868 assign ac97dmar_irq = 1'b0;
869 assign ac97dmaw_irq = 1'b0;
870
871 assign ac97_sout = 1'b0;
872 assign ac97_sync = 1'b0;
873
874 assign ac97bus_adr = 32'bx;
875 assign ac97bus_cti = 3'bx;
876 assign ac97bus_we = 1'bx;
877 assign ac97bus_cyc = 1'b0;
878 assign ac97bus_stb = 1'b0;
879 assign ac97bus_dat_w = 32'bx;
880 `endif
881
882 //---------------------------------------------------------------------------
883 // Programmable FPU
884 //---------------------------------------------------------------------------
885 `ifdef ENABLE_PFPU
886 pfpu #(
887         .csr_addr(4'h5)
888 ) pfpu (
889         .sys_clk(sys_clk),
890         .sys_rst(sys_rst),
891         
892         .csr_a(csr_a),
893         .csr_we(csr_we),
894         .csr_di(csr_dw),
895         .csr_do(csr_dr_pfpu),
896         
897         .irq(pfpu_irq),
898         
899         .wbm_dat_o(pfpubus_dat_w),
900         .wbm_adr_o(pfpubus_adr),
901         .wbm_cyc_o(pfpubus_cyc),
902         .wbm_stb_o(pfpubus_stb),
903         .wbm_ack_i(pfpubus_ack)
904 );
905
906 `else
907 assign csr_dr_pfpu = 32'd0;
908
909 assign pfpu_irq = 1'b0;
910
911 assign pfpubus_dat_w = 32'hx;
912 assign pfpubus_adr = 32'hx;
913 assign pfpubus_cyc = 1'b0;
914 assign pfpubus_stb = 1'b0;
915 `endif
916
917 //---------------------------------------------------------------------------
918 // Texture Mapping Unit
919 //---------------------------------------------------------------------------
920 `ifdef ENABLE_TMU
921 tmu2 #(
922         .csr_addr(4'h6),
923         .fml_depth(`SDRAM_DEPTH)
924 ) tmu (
925         .sys_clk(sys_clk),
926         .sys_rst(sys_rst),
927
928         .csr_a(csr_a),
929         .csr_we(csr_we),
930         .csr_di(csr_dw),
931         .csr_do(csr_dr_tmu),
932
933         .irq(tmu_irq),
934
935         .wbm_adr_o(tmumbus_adr),
936         .wbm_cti_o(tmumbus_cti),
937         .wbm_cyc_o(tmumbus_cyc),
938         .wbm_stb_o(tmumbus_stb),
939         .wbm_ack_i(tmumbus_ack),
940         .wbm_dat_i(tmumbus_dat_r),
941
942         .fmlr_adr(fml_tmur_adr),
943         .fmlr_stb(fml_tmur_stb),
944         .fmlr_ack(fml_tmur_ack),
945         .fmlr_di(fml_tmur_dr),
946
947         .fmldr_adr(fml_tmudr_adr),
948         .fmldr_stb(fml_tmudr_stb),
949         .fmldr_ack(fml_tmudr_ack),
950         .fmldr_di(fml_tmudr_dr),
951
952         .fmlw_adr(fml_tmuw_adr),
953         .fmlw_stb(fml_tmuw_stb),
954         .fmlw_ack(fml_tmuw_ack),
955         .fmlw_sel(fml_tmuw_sel),
956         .fmlw_do(fml_tmuw_dw)
957 );
958
959 `else
960 assign csr_dr_tmu = 32'd0;
961
962 assign tmu_irq = 1'b0;
963
964 assign tmumbus_adr = 32'hx;
965 assign tmumbus_cti = 3'bxxx;
966 assign tmumbus_cyc = 1'b0;
967 assign tmumbus_stb = 1'b0;
968
969 assign fml_tmur_adr = {`SDRAM_DEPTH{1'bx}};
970 assign fml_tmur_stb = 1'b0;
971
972 assign fml_tmudr_adr = {`SDRAM_DEPTH{1'bx}};
973 assign fml_tmudr_stb = 1'b0;
974
975 assign fml_tmuw_adr = {`SDRAM_DEPTH{1'bx}};
976 assign fml_tmuw_stb = 1'b0;
977 assign fml_tmuw_sel = 8'bx;
978 assign fml_tmuw_dw = 64'bx;
979 `endif
980
981 //---------------------------------------------------------------------------
982 // Ethernet
983 //---------------------------------------------------------------------------
984 `ifdef ENABLE_ETHERNET
985 wire phy_tx_clk_b;
986 AUTOBUF b_phy_tx_clk(
987         .I(phy_tx_clk),
988         .O(phy_tx_clk_b)
989 );
990 wire phy_rx_clk_b;
991 AUTOBUF b_phy_rx_clk(
992         .I(phy_rx_clk),
993         .O(phy_rx_clk_b)
994 );
995 minimac #(
996         .csr_addr(4'h9)
997 ) ethernet (
998         .sys_clk(sys_clk),
999         .sys_rst(sys_rst),
1000
1001         .csr_a(csr_a),
1002         .csr_we(csr_we),
1003         .csr_di(csr_dw),
1004         .csr_do(csr_dr_ethernet),
1005
1006         .wbrx_adr_o(ethernetrxbus_adr),
1007         .wbrx_cti_o(ethernetrxbus_cti),
1008         .wbrx_cyc_o(ethernetrxbus_cyc),
1009         .wbrx_stb_o(ethernetrxbus_stb),
1010         .wbrx_ack_i(ethernetrxbus_ack),
1011         .wbrx_dat_o(ethernetrxbus_dat_w),
1012
1013         .wbtx_adr_o(ethernettxbus_adr),
1014         .wbtx_cti_o(ethernettxbus_cti),
1015         .wbtx_cyc_o(ethernettxbus_cyc),
1016         .wbtx_stb_o(ethernettxbus_stb),
1017         .wbtx_ack_i(ethernettxbus_ack),
1018         .wbtx_dat_i(ethernettxbus_dat_r),
1019
1020         .irq_rx(ethernetrx_irq),
1021         .irq_tx(ethernettx_irq),
1022
1023         .phy_tx_clk(phy_tx_clk_b),
1024         .phy_tx_data(phy_tx_data),
1025         .phy_tx_en(phy_tx_en),
1026         .phy_tx_er(phy_tx_er),
1027         .phy_rx_clk(phy_rx_clk),
1028         .phy_rx_data(phy_rx_data_b),
1029         .phy_dv(phy_dv),
1030         .phy_rx_er(phy_rx_er),
1031         .phy_col(phy_col),
1032         .phy_crs(phy_crs),
1033         .phy_mii_clk(phy_mii_clk),
1034         .phy_mii_data(phy_mii_data)
1035 );
1036 `else
1037 assign csr_dr_ethernet = 32'd0;
1038 assign ethernetrxbus_adr = 32'bx;
1039 assign ethernetrxbus_cti = 3'bx;
1040 assign ethernetrxbus_cyc = 1'b0;
1041 assign ethernetrxbus_stb = 1'b0;
1042 assign ethernetrxbus_dat_w = 32'bx;
1043 assign ethernettxbus_adr = 32'bx;
1044 assign ethernettxbus_cti = 3'bx;
1045 assign ethernettxbus_cyc = 1'b0;
1046 assign ethernettxbus_stb = 1'b0;
1047 assign ethernettxbus_dat_r = 32'bx;
1048 assign ethernetrx_irq = 1'b0;
1049 assign ethernettx_irq = 1'b0;
1050 assign phy_tx_data = 4'b0;
1051 assign phy_tx_en = 1'b0;
1052 assign phy_tx_er = 1'b0;
1053 assign phy_mii_clk = 1'b0;
1054 assign phy_mii_data = 1'bz;
1055 `endif
1056
1057 // TODO
1058 assign phy_clk = 1'b0;
1059
1060 //---------------------------------------------------------------------------
1061 // FastMemoryLink usage and performance meter
1062 //---------------------------------------------------------------------------
1063 `ifdef ENABLE_FMLMETER
1064 fmlmeter #(
1065         .csr_addr(4'ha)
1066 ) fmlmeter (
1067         .sys_clk(sys_clk),
1068         .sys_rst(sys_rst),
1069
1070         .csr_a(csr_a),
1071         .csr_we(csr_we),
1072         .csr_di(csr_dw),
1073         .csr_do(csr_dr_fmlmeter),
1074
1075         .fml_stb(fml_stb),
1076         .fml_ack(fml_ack)
1077 );
1078 `else
1079 assign csr_dr_fmlmeter = 32'd0;
1080 `endif
1081
1082 // TODO
1083 assign vga_sda = 1'b0;
1084 assign vga_sdc = 1'b0;
1085
1086 assign mc_d[3:0] = 4'bz;
1087 assign mc_cmd = 1'bz;
1088 assign mc_clk = 1'b0;
1089
1090 assign usba_spd = 1'b0;
1091 assign usba_oe_n = 1'b0;
1092 assign usba_vp = 1'bz;
1093 assign usba_vm = 1'bz;
1094 assign usbb_spd = 1'b0;
1095 assign usbb_oe_n = 1'b0;
1096 assign usbb_vp = 1'bz;
1097 assign usbb_vm = 1'bz;
1098
1099 assign videoin_sda = 1'bz;
1100 assign videoin_sdc = 1'b0;
1101
1102 assign midi_tx = 1'b0;
1103
1104 assign dmxa_de = 1'b0;
1105 assign dmxa_d = 1'b0;
1106 assign dmxb_de = 1'b0;
1107 assign dmxb_d = 1'b0;
1108
1109 endmodule